Syllabus

Google Meet: HDL, E404 https://meet.google.com/ykb-ptoy-xha　

Course Title: Hardware Description Language (硬體描述語言, using Verilog)

Course No. 53022

Semester: Fall, 2023

Time and Classroom: Thu. 9:05-12:00 (E406)

Credits: 3

Lector: Professor Tsung-Chu Huang (黃宗柱)

Email: tch@cc.ncue.edu.tw

Tel. (04)723-2105 ext. 8384

Website: http://testlab.ncue.edu.tw/tch

NCUE Cloud: https://dlearn.ncue.edu.tw

Cloud:    https://drive.google.com/drive/folders/141If6V7_K0ndAU6K5cDORBqskcYo-uen?usp=sharing  

• Textbook and References

  • Textbook:

    • Samir Palnitkar. "Verilog HDL -- A Guide to Digital Design and Synthesis." 2nd ed., Prentice Hall, ISBN 0-13-044911-3 , 2003.

    • Mark Gordon Arnold. "Verilog Digital Computer Design -- Algorithms into Hardware." ISBN: 0-13-639253-9, Prentice Hall PTR, 1999. (中譯版:  楊紹聖等編, 全華, ISBN: 9572131176)

    　

• Schedule and Contents

  　

  Mn	Topics	Week	Date	Lec.	Content	Lab	Content	Video
  1st	Verilog Grammar and Directives, ALU	01	09/15	01	Overview	01	N-bit Adder	MP4
  		02	09/22	02	View, Level, Hierarchy	02	Review N-bit Adder, FFs	MP4
  		03	09/29	03	Type, Op, 4Mdl,8Blks	03	Boolean, FA, 7Seg	MP4
  		04	10/06	04	ASM, Serial Multipliers	04	Counter, FDiv, Clock, Snake	MP4
  2nd	Quartus II Design Flow, CU	05	10/13	05	Exam, FSM	05	Button-press time	MP4
  		06	10/20	06	Morse Codes	06	Morse Codes	MP4
  		07	10/27	07	UART	07	UART	MP4
  		08	11/03	08	Setup-Hold Timing	08	Multiplication timing closure	MP4
  3rd	EDA Scripting, IO, MU	09	11/10	09	Exam, Fixed-Point	09	Practice	-
  		10	11/17	10	Booth Multipliers, IEEE754	10	Booth EDA Scripts	MP4
  		11	11/24	11	CORDIC, ROM	11	CORDIC EDA Scripts	MP4
  		12	12/01	-	(Athletic Games)	-	-	-
  		13	12/08	12	ROM &RAM	12	Memory Controller	MP4
  4th	CPU design	14	12/15	13	Intro CPU Design, SAP3x5	13	SAP3x5	MP4
  		15	12/22	14	SAP444	14	SAP444	MP4
  		16	12/29	15	Introduction to MIPS	15	Tiny MIPS	MP4
  		17	01/05	16	SPIM and Implementation	16	SPIM Assembly	MP4
  		18	01/12	17	Bonus Proj.	Exam	Practice	-

   (click Lec. number for linking to the lectures and go to the cloud for labs.)

   (Find MP4 lectures at .https://dlearn.ncue.edu.tw)

   

• Criteria

  • Homework and Quiz: 5% x 4

  • Paper Exam: 20% x 2

  • Practice Test: 20% x 2

  • Bonus Term Project: -10%~+20%

• Links

  • http://www.altera.com

  • http://www.xilinx.com

  • http://www.synapticad.com

  • https://ocw.mit.edu/courses/6-111-introductory-digital-systems-laboratory-spring-2006/pages/lecture-notes/

  • Open cores: http://www.opencores.org

  • Examples provided by Altera: http://www.altera.com/support/examples/verilog/verilog.html

  • CPU Design -- Howto

  • http://residence.educities.edu.tw/oldfriend/page52.htm

  • Verilog Tutorials at Youtube

  • Quartus II Tutorial (from Schematics) at Youtube

  • Verilog HDL at Youtube

  • Online Verilog-1995 Quick Reference Guide

  • Stanford's Verilog Quick Guide

  • UVIC's Verilog Quick reference Card

  • Verilog Wiki

  • The IEEE Verilog 1364-2001 Standard What's New, and Why You Need It.

  • IEEE Standard 1364-2001