Recent Publication

A) Journal Papers

[1] T.-C. Huang. Efficient and Dependable Approximate Computing of Residue Number System for Neural Network Acceleration. submitted to IEEE Design & Test. Nov. 4, 2020.

[2] T.-C. Huang. Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. IEEE Communications Letters, vol.19, no.6, pp.917-920, Jun. 2015. [SCI, 2014 IF=1.463, TELECOMM](MOST-103-2221-E-018-032-)

[3] T.-C. Huang. Cluster-Error Correction for Through-Silicon Vias in 3D ICs. IET Electronics Letters, vol. 51, no.3, pp.289-290, Feb. 2015. [SCI, IF=1.068] (MOST-103-2221-E-018-032-)

 

B) Conference Papers

[1]  T.-Y. Chen, C.-D Tsai, H.-W. Fu, Y.-C. Yang and T.-C. Huang. "Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.

[2]  H.-W. Fu, T.-Y. Chen, C.-D. Tsai, M.-W. Shen and T.-C. Huang. "AN-Coded Redundant  Residue Number System for Reliable Neural Networks," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.

[3]  C-S. Lin, J. Huang. P.-S. Chang, C.-Y. Tsai and T.-C. Huang. "SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.

[4]  C.-D. Tsai, T.-Y. Chen, H.-W. Fu and T.-C. Huang. "TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network," 2021 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS2021), virtual, June 7, 2021.

[5]  L.-Y. Lin, J. Schroff, T.-P. Lin and T.-C. Huang. "Residue Number System Design Automation for Neural Network Acceleration," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.

[6]  W.-C. Yang, S.-Y. Lin and T.-C. Huang. "Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.

[7]  L.-Y. Lin, J. Schroff, C.-C. Liang and T.-C. Huang. "Approximate Computing for Batch Learning in Neural Network," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.

[8]  L.-Y. Lin, J. Schroff, T.-P. Lin and T.-C. Huang. Efficient Approximate Computing of Residue Number System for Neural Network Acceleration. TICD 2020 VLSI Design/CAD Symposium, Kaohsiung, Aug. 4-7, 2020.

[9]  J. Huang, C.-S. Lin and T.-C. Huang. SAFER: Single Aging-Factor Enhanced Rings as Data Annotators and Early Warners of On-line Aging Monitoring for Automotive SoCs. TICD 2020 VLSI Design/CAD Symposium, Kaohsiung, Aug. 4-7, 2020.

[10] J. Huang and T.-C. Huang. Precompensation, BIST and Analogue Berger Codes for Reliable Neuromorphic RRAM. TICD the 14th VLSI Test Technology Workshop, Kaohsiung, July 27-29, 2020.

[11] J. Huang, C.-S. Lin and T.-C. Huang. SAFER: Single Aging-Factor-Enhanced Ring Oscillators for Aging Annotation and Early Warning  for Co-Learning in On-Line Aging Monitors. TICD the 14th VLSI Test Technology Workshop, Kaohsiung, July 27-29, 2020.

[12] T.-C. Huang. Self-Checking Residue Number System for Low-Power Reliable Neural Network. Proceedings of The 28th IEEE Asian Test Symposium, pp.37-42, Kolkata, Dec 12,.2019.

[13] T.-C. Huang, C.-H. Chiang and M.-H.. Lin, "Low-Cost and Fast Design of Precise Activation Functions in Neural Network," 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Yilan, Taiwan, May 21, 2019.

[14]  C.-H. Chiang, L.-Y. Lin, M.-H. Lin and T.-C. Huang. Accelerating Neural Network with Totally Self-Checking through Sigmoidal Activation Functions. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.

[15]  W.-C. Yang and T.-C. Huang. Optimized Piecewise-Linear Lookup Table without Multipliers for Activation Functions in Neural Network. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.

[16]  Y.-T. Chang, D.-Y. Wu, J. Huang, J.-C. Jhang and T.-C. Huang. Error-Resilient Neuromorphic RRAM. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.

[17]  C.-H. Chiang, W.-C. Yang, L.-Y. Lin, M.-H. Lin and T.-C. Huang. Low-Power Compact Fast and Reliable Neural Network Based on Redundant Residue Number System. TICD the 13th VLSI Test Technology Workshop, Chiayi, July 2019.

[18]  Yu-Teng Chang, Dong-Ying Wu, Jing Huang, Jia-Cheng Jhang and Tsung-Chu Huang. Two-Dimensional Analogue Berger Codes for Error-Resilient Neuromorphic RRAM. TICD the 13th VLSI Test Technology Workshop, Chiayi, July 2019.

[19]  T.-C. Huang and J. Schroff (2018, Oct). Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. The 27th IEEE Asian Test Symposium, Hefei, pp.173-178, Oct. 2018.

[20]  J. Schroff, D.-Y. Wu, J. Huang, Y.-R. Chen, W. Lee and T.-C. Huang. Linear-System-based Built-In Self-Test for Configurable Neuromorphic RRAM. 2018 VLSI Design/CAD Symposium, Tainan, Aug. 2018..

[21]  Y.-T. Chang, J. Schroff, D.-Y. Wu, J. Huang and T.-C. Huang. Pre-degradation Compensation and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. 2018 VLSI Design/CAD Symposium, Tainan, Aug. 2018.

[22] C.-W. Lin and T.-C. Huang. Online defect tolerance scheme with CORDIC-based FFT of Dual Modular Redundancy application. 2018 the 12th VLSI Test Technology Workshop, Taichung, July 2018.

[23]D.-Y. Wu, J. Schroff, J. Huang, Y.-Ren Chen, W. Lee and T.-C. Huang. Compensation and BIST of Crossbar-based RRAM in Configurable Neural Network. 2018 the 12th VLSI Test Technology Workshop, Taichung, July 2018.

[24]   Y.-S. Li, M.-J. Luo and T.-C. Huang. Multi-Cluster Error Correction for TSVs in 3D-ICs. 2018 the 12th VLSI Test Technology Workshop, Taichung, Jul. 2018.

[25]   Y.-T. Chang, J. Schroff, D.-Y. Wu, J. Huang and T.-C. Huang. Precompensated Analogue Berger Codes for Self-Healing of Neuromorphic RRAM in Neural Network. 2018 the 12th VLSI Test Technology Workshop, Taichung, Jul. 2018.

[26]   Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. 2017 VLSI Design / CAD Symposium, Pingtung, Aug. 2017.

[27] Y.-S. Li, S.-N. H. and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, Jul. 2017.

[28] Y.-S. Li, S.-N Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. TICD VLSI Design/CAD Symposium, Pingtung, Aug. 2017.

[29] Y.-C. Lin and T.-C. Huang. Multiple-TSV Schemes for Lagging-Defect Tolerant Clock-Delivery in 3D ICs. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.

[30] Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.

[31] T.-C. Huang and S.-Y. Huang. Doubling Schemes for Defect-Tolerant Clock-Delivery TSVs in Automotive 3D-ICs. IEEE ART joined with The 46th International Test Conference, Fort Worth, 2016.

[32] Y.-C. Lin and T.-C. Huang. A Multiple-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2017.

[33] Jhen-Sing Chen and T.-C. Huang. A Dual-Symptom Aging Monitor for Critical Data Interconnects. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2016.

[34] Kun-Yuan Li Mong-Lin Li Tsung-Chu Huang A Defect-Tolerant Multi-TSV Structure and Placement for Power-Grids in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug., 2016.

[35] Jhen-Sing Chen and T.-C. Huang. A Dual-Symptom Aging Monitor for Data-Delivery TSVs in 3D-ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[36] Y.-C. Lin and T.-C. Huang. A Double-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[37] Kun-Yuan Li, Mong-Lin Li and Tsung-Chu Huang. A Defect-Tolerant Structure and Placement for Power-Delivery TSVs in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[38] Bo-Shun Lin and Tsung-Chu Huang. A Precomputation-based Remapping Architecture for Hypercube-based Multi-dimensional Memory Repairing. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[39]  Tsung-Chu Huang. ECMO: Error Clock-TSV Mending On-the-fly. IEEE The 45th International Test Conference, PO1.6, Anaheim, Oct. 6, 2015. (EI)

[40]  Tsung-Chu Huang. Cluster Error Correction and On-Line Repair for Real-Time TSV Array. IEEE The 6th Asia Symposium on Quality Electronic Design, 3B-3, Kuala Lumpur, Aug. 5, 2015. (EI)

C) Patents

        ► Issued Patents

[1] Tsung-Chu Huang. 矽穿孔自我繞線電路及其繞線方法(Through-Silicon Via Self-Routing Circuit and Routing Method thereof). ROC Patent No.I456706, Oct. 11, 2014.

[2] Tsung-Chu Huang. Through-silicon via self-routing circuit and routing method thereof. US Patent No.8,754,704, June 17, 2014.

[3] Tsung-Chu Huang. 記憶體位址重新映射裝置與修復方法(Memory Address Remapping Apparatus and Repairing Method thereof). ROC Patent No.I439857, June 1, 2014.

[4] Tsung-Chu Huang. 動態隨機存取記憶體之內容可定址記憶單元(DRAM-based Content Addressable Memory Cell). ROC Patent No.I440033, June 1, 2014.

[5] Tsung-Chu Huang. 大小比較器以及內含此比較器之內容可定址記憶體與不等寬色譜器(Magnitude Comparator, Magnitude Comparator Based Content Addressable Memory Cell, and Non-Equal Bin-Width Histogrammer). ROC Patent No.I409696, Sep. 21, 2013.

[6] Tsung-Chu Huang. Memory address remapping architecture and repairing method thereof. US Patent No.8,522,072, Aug. 27, 2013.

[7] Tsung-Chu Huang. 利用中央極限定理之常態分佈亂數產生器及其亂數產生方法(A Normal Distributed Random Number Generator by Using the CLT and the Random Number Generating Method thereof). ROC Patent No. I387921, Mar. 1, 2013. (NSC-94-2215-E-018-007-)

[8] Tsung-Chu Huang. 伯格反相碼之編解碼方法及其編碼器與檢查器電路(Berger Invert Code Encoding and Decoding Method). ROC Patent No. I377794, Nov. 21, 2012. (NSC-94-2215-E-018-007-)

[9] Tsung-Chu Huang. Magnitude comparator, magnitude comparator based content addressable memory cell, and non-equal bin width histogrammer. US Patent No.8,253,546, Aug. 28, 2012.(NSC-99-2221-E-018-025-)

[10] Tsung-Chu Huang. 低功率低面積全數位隨機抖動產生器(Low-Power Low-Area All-Digital Random Jitter Generator). ROC Patent No. I362833, Apr. 21, 2012. (NSC-94-2215-E-018-007-)

 

        ► Patents under Pending

[1] Tsung-Chu Huang. 電路老化監測系統及其方法(Circuit Aging Monitor System and Method thereof). ROC Patent, App. No.109138488, Nov. 4, 2020.

 

 

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