Recent Publication

A) Journal Papers

[1] Tsung-Chu Huang. Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. IEEE Communications Letters, vol.19, no.6, pp.917-920, Jun. 2015. [SCI, 2014 IF=1.463, TELECOMM](MOST-103-2221-E-018-032-)

[2] Tsung-Chu Huang. Cluster-Error Correction for Through-Silicon Vias in 3D ICs. IET Electronics Letters, vol. 51, no.3, pp.289-290, Feb. 2015. [SCI, IF=1.068] (MOST-103-2221-E-018-032-)

[3] Yen-Chieh Huang and Tsung-Chu Huang. Dependable embedded memory for intelligent systems. Springer Verlag, Lecture Notes in Electrical Engineering, vol.234 LNEE, pp.573-579 , 2013. [EI, IF=0.13] (MOST-102-2221-018-030-)

[4] Tsung-Chu Huang. High-Performance Built-In Self-Routing for Through Silicon Vias. IET Electronics Letters, vol.48, no.9, pp.480-481, May 2012. (with invited feature, J. Baldwin. Routing for Moore, p.468) [SCI, 2011 IF=1.068, 131/245, EEE] (NSC-101-2221-E-018-036-)

[5] Tsung-Chu Huang. High-Yield Performance-Efficient Redundancy Analysis for 2D Memory. Science China: Information Science, 54(8):1663-1676 , Springer, Aug. 2011. [SCI, 2011 IF=0.644, 99/128, CS INFO SYS] (NSC-100-2221-E-018-014-)

[6] Tsung-Chu Huang. Multi-Valued Equal-Weight Codes for Self-Checking and Matching. IEEE Communications Letters, vol. 13, no. 12, pp.947-949, Dec. 2009. [SCI, 2009 IF=1.140, 23/77, TELECOMM] (NSC-99-2221-E-018-025-)

[7] Tsung-Chu Huang. A Low-Power Dependable Berger Code for Fully Asymmetric Communication. IEEE Communications Letters, vol. 12, no. 10, pp.773-775, Oct. 2008. [SCI, 2008 IF=1.232, 22/67, TELECOMM] (NSC-99-2221-E-018-025-)

 

B) Conference Papers

[1] Y.-S. Li, S.-N Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. TICD VLSI Design/CAD Symposium, Pingtung, Aug. 1, 2017.

[2] Y.-C. Lin and Tsung-Chu Huang. Multiple-TSV Schemes for Lagging-Defect Tolerant Clock-Delivery in 3D ICs. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.

[3] Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.

[4] T.-C. Huang and S.-Y. Huang. Doubling Schemes for Defect-Tolerant Clock-Delivery TSVs in Automotive 3D-ICs. IEEE ART joined with The 46th International Test Conference, Fort Worth, 2016. (EI)

[5] Yu-Chien Lin and Tsung Chu Huang. A Multiple-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2017.

[6] Jhen-Sing Chen and Tsung-Chu Huang. A Dual-Symptom Aging Monitor for Critical Data Interconnects. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2017.

[7] Yu-Chien Lin and Tsung Chu Huang. A Double-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July 13, 2016.

[8] Jhen-Sing Chen and Tsung-Chu Huang. A Dual-Symptom Aging Monitor for Data-Delivery TSVs in 3D-ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July 13, 2016.

[9] Kun-Yuan Li, Mong-Lin Li and Tsung-Chu Huang. A Defect-Tolerant Structure and Placement for Power-Delivery TSVs in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July 13, 2016.

[10] Bo-Shun Lin and Tsung-Chu Huang. A Precomputation-based Remapping Architecture for Hypercube-based Multi-dimensional Memory Repairing. TICD the 10th VLSI Test Technology Workshop, Nantou, July 13, 2016.

[11] Tsung-Chu Huang. ECMO: Error Clock-TSV Mending On-the-fly. IEEE The 45th International Test Conference, PO1.6, Anaheim, Oct. 6, 2015. (EI)

[12]  Tsung-Chu Huang. Cluster Error Correction and On-Line Repair for Real-Time TSV Array. IEEE The 6th Asia Symposium on Quality Electronic Design, 3B-3, Kuala Lumpur, Aug. 5, 2015. (EI)

[13] Yi-Sheng Lin, Lung-Yun Chang and Tsung-Chu Huang. Zero-Latency Cluster-Error Correction for TSVs in 3D ICs.  TICD VLSI Design and CAD Symposium, Hualian, Aug. 4, 2015.

[14] Yi-Sheng Lin, Lung-Yun Chang, Yu-Jen Li and Tsung-Chu Huang. Zero-Latency Cluster-Error Correction for TSV Arrays in Stacked Memory. The 9th VLSI Test Technology Workshop, 4-1, Tainan, July 14, 2015.

[15] Wei-Ting Liu and Tsung-Chu Huang. An On-Line Monitoring and Repairing Architecture for Clock TSVs in 3D-ICs. The 9th VLSI Test Technology Workshop, 4-4, Tainan, July 14, 2015.

[16]   Tsung-Chu Huang and Yu-Yi Chen. Low-Latency Error-Correction Decoding for Clustered TSVs. TICD VLSI Design and CAD Symposium, P2, Taichung, Aug. 2014.

[17]   Hsuan-Yu Fu, Sheng-An Lu, and Tsung-Chu Huang. An Iterative Logic Array for Selecting TSVs in 3D ICs. TICD VLSI Design and CAD Symposium, S07-09, Taichung, Aug. 2014.

[18]   Hsuan-Yu Fu, Sheng-An Lu, and Tsung-Chu Huang. Multi-way Built-In Self-Router for 3D ICs. Workshop on Consumer Electronics, Nov. 2014.

[19]   Yen-Chieh Huang and Tsung-Chu Huang. Dependable Embedded Memory for Intelligent Systems. Proc. in International Conference on Intelligent Technologies and Engineering Systems, B5-1, Changhua, Taiwan, Dec. 13-15. 2012.

[10]  Sheng-An Lu, Yi-Jing Wu and Tsung-Chu Huang. Dependable Inter-Chip Communications via Built-In Self-Routers. In Proc. 2012 National Symposium on Telecommunications, B2-5, Changhua, Nov. 16, 2012.

[21]  Sheng-An Lu Yi-Jing Wu Tsung-Chu Huang. Built-In Self-Routers for Repairing TSVs in 3D ICs. In Proc. the 6th VLSI Test Technology Workshop, Yilan, July 10, 2012.

[22]  Kuei-Yeh Lu, Yen-Chieh Huang, Jian-Ci Wang and Tsung-Chu Huang. EXTREMES: External Repair for Clustered Faults of Memory to the Extremes. In Proc.of the 5th VLSI Test Technology Workshop, pp.89-94, Nantao, July 15, 2011.

[23]  Yun-Ping Wang and Tsung-Chu Huang. Magnitude-Comparator-Based CAM for Efficient Hybrid Routers. In Proc. Electronic Technology Symposium, Kaohsiung, EO-01, June 10, 2011. (NSC-99-2221-E-018-025-)

[24]  Yu-Ching Wen and Tsung-Chu Huang. Searching-Once Single-Transistor MLC Flash CAM. In Proc. of the 6th Intelligent Living Technology Conference, ISBN.987-957-21-8031-0, pp.975-980, June 5, 2011. (NSC-99-2221-E-018-025-)

[25]  Yu-Ting Lin and Tsung-Chu Huang. A Low-Cost High-Speed Constant-Weight Code Checker. In Proc. Conf. on Electronic Communication and Applications, pp.480-485, Kaohsiung, May 20, 2011. (NSC-99-2221-E-018-025-)

[26] Tsung-Chu Huang, Kuei-Yeh Lu and Yen-Chieh Huang. HYPERA: High-Yield Performance-Efficient Redundancy Analysis. In Proc. IEEE 19th Asian Test Symposium, pp.231-235 Shanghai, Dec. 1-4, 2010.[EI](NSC-99-2221-E-018-025-)

[27] Kwei-Yeh Lu, Yen-Chieh Huang and Tsung-Chu Huang. A High-Yield Architecture for Memory Repairing. In Proc.2010 Workshop on Consumer Electronics, pp.835-842, Tainan, Nov. 5, 2010.

[28] Yun-Ping Wang and Tsung-Chu Huang. Comparator-Based Content-Addressable Memory and Application for a Novel IP Router. In Proc.2010 Workshop on Consumer Electronics, pp.79-86, Tainan, Nov. 5, 2010.

[29] Yu-Ching Wen and Tsung-Chu Huang. Low-Cost Fast MLC Flash CAM. In Proc.2010 Workshop on Consumer Electronics, pp.62-70, Tainan, Nov. 5, 2010.

[30]  Pin-Chung Chen, Sheng-Jie Fan, Yun-Ping Wang, Yung-Sheng Kao and Tsung-Chu Huang. Area-Efficient High Goodness-of-Fit Noise Generator for Communication Test. The 4th VLSI Test Technology Workshop, S3-2, Yilan, Aug. 19, 2010.

[31] Wei-Ning Hsu, Yu-Ching Wen and Tsung-Chu Huang. Dependable and Area-Efficient Equal-Weight Coded Content-Addressable Memory. The 21th VLSI Design and CAD Symposium, pp.135-138, Kaohsiung, Taiwan, Aug. 5, 2010. 

[32] Pin-Chong Chen, Sheng-Jie Fan, Tsung-Chu Huang. Distribution-Compensable Random-Number Generator for High-Goodness-of-Fit Jitter Generator. In Proc. 2010 Electronic Technology Symposium, Session BO-05, Kaohsiung, June 18, 2010.

[33] Sheng-Jie Fan, Pin-Chong Chen and Tsung-Chu Huang. Distribution-Compensable Jitter Generator for Bit-Error-Rate Test. In Proc. of the 4th Conf. on Integrated Opto-Mechatronic Technology and Intellectual Property Rights, pp.87-96, Taipei, May 12,2010.

[34] Wei-Ning Hsu, Tsu-Hsin Wu and Tsung-Chu Huang. Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency. IEEE International Workshop on Memory Technology, Design and Testing, Hsinchu, pp.38-41, Aug. 31, 2009.

[35] Yi-Hsien Chou, Tsu-Hsin Wu, Pin-Chung Chen and Tsung-Chu Huang. Distribution-Compensable Jitter Generator for Communication Test. The 20th VLSI Design and CAD Symposium, Hualian, Taiwan, pp.574-577, Aug. 5, 2009.

[36] Yi-Hsien Chou, Tsu-Hsin Wu and Tsung-Chu Huang. Low-Cost CLT-based Random Number Generator for Communication Test. The 3rd VLSI Test Technology Workshop, pp.79-82, Nantao, July 16, 2009.

[37] Yi-Hsian Chou, Sheng-Jie Fen, Tsu-Hsin Wu and Tsung-Chu Huang. Low-Cost Fast Distribution-Programmable Jitter Generators for Communication Test. In Proc. of the 4th Intelligent Living Technology Conference, ISBN.987-957-21-7031-1, pp.837-843, June 5, 2009.

[38] Choa-Nan Liu, Shih-Chuan Lo and Tsung-Chu Huang. Inverting Techniques for Low-Power Dependable Fully-Asymmetric Communication and Storage Systems. In Proc. of the 4th Intelligent Living Technology Conference, ISBN.987-957-21-7031-1, pp.896-901, June 5, 2009. 

[39] Hsiao-Han Hou, Yi-Hsien Chou and Tsung-Chu Huang. A Low-Cost and Fast Normal-Distribution Random Number Generator. PAL Consortium Conference on Innovation Applications of System Prototyping and Circuit Design, pp.130-134, Oct. 17, 2008.

[40] Choa-Nan Liu, Shun-Dao Lin and Tsung-Chu Huang. Berger Inver Codes: A Low-Power Dependable Code for Fully Asymmetric Communication. PAL Consortium Conference on Innovation Applications of System Prototyping and Circuit Design, pp.336-340, Oct. 17, 2008.

[41] Cheng-Han Yang, Yi-Hsian Chou and Tsung-Chu Huang. Area-Efficient True One-Period Delayline for Cycle-to-Cycle Jitter Measurement. The 19th VLSI Design/CAD Symposium, Hualian, Taiwan, pp.280-283, 7 Aug. 2008.

[42] Chih-Jong Chen and Tsung-Chu Huang. MTCMOS SRAM Design for Data-Retention and High-Resolution Current Test. The 2nd VLSI Test Technology Workshop, pp.20-25, Tainan, July 17, 2008.

[43]  Cheng-Han Yang, Yi-Hsian Chou, and Tsung-Chu Huang. Area-Efficient True One-Period Delay Jitter Measurement. The 2nd VLSI Test Technology Workshop, pp.83-86, Tainan, July 18, 2008.

[44]  Hsin-Ling Chen, Ling Li, Choa-Nan Liu, and Tsung-Chu Huang. A Novel Adaptive-Data-Retention CMOS Logic Structure for IDDS Test. The 2nd VLSI Test Technology Workshop, pp.109-114, Tainan, July 18, 2008.

 

C) Patents

        ► Issued Patents

[1] Tsung-Chu Huang. 矽穿孔自我繞線電路及其繞線方法(Through-Silicon Via Self-Routing Circuit and Routing Method thereof). ROC Patent No.I456706, Oct. 11, 2014.

[2] Tsung-Chu Huang. Through-silicon via self-routing circuit and routing method thereof. US Patent No.8,754,704, June 17, 2014.

[3] Tsung-Chu Huang. 記憶體位址重新映射裝置與修復方法(Memory Address Remapping Apparatus and Repairing Method thereof). ROC Patent No.I439857, June 1, 2014.

[4] Tsung-Chu Huang. 動態隨機存取記憶體之內容可定址記憶單元(DRAM-based Content Addressable Memory Cell). ROC Patent No.I440033, June 1, 2014.

[5] Tsung-Chu Huang. 大小比較器以及內含此比較器之內容可定址記憶體與不等寬色譜器(Magnitude Comparator, Magnitude Comparator Based Content Addressable Memory Cell, and Non-Equal Bin-Width Histogrammer). ROC Patent No.I409696, Sep. 21, 2013.

[6] Tsung-Chu Huang. Memory address remapping architecture and repairing method thereof. US Patent No.8,522,072, Aug. 27, 2013.

[7] Tsung-Chu Huang. 利用中央極限定理之常態分佈亂數產生器及其亂數產生方法(A Normal Distributed Random Number Generator by Using the CLT and the Random Number Generating Method thereof). ROC Patent No. I387921, Mar. 1, 2013. (NSC-94-2215-E-018-007-)

[8] Tsung-Chu Huang. 伯格反相碼之編解碼方法及其編碼器與檢查器電路(Berger Invert Code Encoding and Decoding Method). ROC Patent No. I377794, Nov. 21, 2012. (NSC-94-2215-E-018-007-)

[9] Tsung-Chu Huang. Magnitude comparator, magnitude comparator based content addressable memory cell, and non-equal bin width histogrammer. US Patent No.8,253,546, Aug. 28, 2012.(NSC-99-2221-E-018-025-)

[10] Tsung-Chu Huang. 低功率低面積全數位隨機抖動產生器(Low-Power Low-Area All-Digital Random Jitter Generator). ROC Patent No. I362833, Apr. 21, 2012. (NSC-94-2215-E-018-007-)

 

        ► Patents under Pending

[1] Tsung-Chu Huang. Low-Spike Wakeup-Accelerated Power-Gating Logic Structure and Test Method Thereof. ROC Patent, Disc. No.200834294, Feb. 9, 2007.

[2] Tsung-Chu Huang. Berger Invert Code Encoding and Decoding Method. US Patent, No. US20100095192 A1, Mar. 13, 2009.

 

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