Recent Publication
A)
Journal Papers
[1] T.-C. Huang. Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. IEEE Communications Letters, vol.19, no.6, pp.917-920, Jun. 2015. [SCI, 2014 IF=1.463, TELECOMM](MOST-103-2221-E-018-032-)
[2] T.-C. Huang. Cluster-Error Correction for Through-Silicon Vias in 3D ICs. IET Electronics Letters, vol. 51, no.3, pp.289-290, Feb. 2015. [SCI, IF=1.068] (MOST-103-2221-E-018-032-)
B) Conference Papers
[1] T. -Y. Chen, Z. -Y. Wang and T. -C. Huang, "TCB Convolution: Ternary-Coded Binarized Convolutions with Fixed-Point Filters," 2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), PingTung, Taiwan, 2023, pp. 95-96, doi: 10.1109/ICCE-Taiwan58799.2023.10226986.
[2] C. Lin, H. Hsu and T. -C. Huang, "Redundant Lagrange Interpolation for Fault-Tolerant Winograd Convolution," 2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), PingTung, Taiwan, 2023, pp. 97-98, doi: 10.1109/ICCE-Taiwan58799.2023.10226694.
[3] W.-J. Huang, H.-W. Fu, T.-C. Huang. "AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network Accelerators," Proceedings of The 31st IEEE Asian Test Symposium, pp.132-137, Taichung, Nov, 23. 2022.
[4] Y. -H. Kao, C. -C. Liu, Y. -W. Ding and T. -C. Huang, "An Efficient Fault-Tolerant Winograd Convolution for Convolutional Neural Networks," 2022 IET International Conference on Engineering Technologies and Applications (IET-ICETA), 2022, pp. 1-2, Oct. 15, 2022.
[5] W.-J. Huang, H.-W. Fu, and T.-C. Huang. "AN-HRNS: AN-Coded Hierarchical Residue Number System for Neural Network Acceleration and Reliability," TICD 2020 VLSI Design/CAD Symposium, Virtual (NTHU), Aug. 3, 2022.
[6] K.-Y. Huang, C.-D. Tsai, and T.-C. Huang. "2DAN-BNN: Two-Dimensional Error Location for AN-Code Decoders in Binarized Neural Networks ," TICD 2020 VLSI Design/CAD Symposium, Virtual (NTHU), Aug. 3, 2022.
[7] Kuan-Yu Huang, Jettae Schroff, Cheng-Di Tsai and T.-C. Huang. "2DAN-BNN: Two-Dimensional AN-Code Decoders for Binarized Neural Networks," IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), pp.147-148, Taipei, Taiwan, July 6-8, 2022 .
[8] Jyun-Xin Ke, Siang-En Chou, Ting-Yu Chen and T.-C. Huang. "SPINDLE: Self-Pretrainable In-situ Normalizer for Deep Learning Error Function," IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), pp.59-61, Taipei, Taiwan, July 6-8, 2022.
[9] C.-D. Tsai, H.-W. Fu, T.-Y. Chen and T.-C. Huang. "TAIWAN Online: Test AI With AN Codes for Automotive Chips," IEEE 2021 International Test Conference -- Asia, Virtual (Shanghai), Aug. 18-20, 2021.
[10] C.-D. Tsai, T.-Y. Chen, C.-Y. Tsai, P.-S. Chang and T.-C. Huang. "TCBNN: Ternary-Coded Binarized Neural Network with Per-Neuron Single-Arithmetic-Fault Tolerance," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.
[11] C.-S. Lin, P.-S. Chang, C.-Y. Tsai and T.-C. Huang. "SAFER and SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for High-Correlation Early Warning in Online Aging Monitors of Automotive Chips," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.
[12] H.-W. Fu, M.-W. Shen and T.-C. Huang. "AN-RNSNN: AN-Coded Redundant Residue Number System for Neural Network Acceleration and Reliability," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.
[13] T.-Y. Chen, C.-D. Tsai, H.-W. Fu, Y.-C. Yang and T.-C. Huang. "Error Correctable Range-Addressable Lookup for Any Activation Function of Neural Networks," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.
[14] C.-D. Tsai, T.-Y. Chen, C.-Y. Tsai, P.-S. Chang and T.-C. Huang. "Per-Neuron Single-Arithmetic-Fault Correctable Ternary-Coded Binarized Neural Network," TICD the 15th VLSI Test Technology Workshop, Virtual (Kaohsiung), July 19-20, 2021.
[15] H.-W. Fu, M.-W. Shen and T.-C. Huang. "AN-Coded Redundant Residue Number System for Neural Network Acceleration and Reliability," TICD the 15th VLSI Test Technology Workshop, Virtual (Kaohsiung), July 19-20, 2021.
[16] T.-Y. Chen, C.-D Tsai, H.-W. Fu, Y.-C. Yang and T.-C. Huang. "Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.
[17] H.-W. Fu, T.-Y. Chen, C.-D. Tsai, M.-W. Shen and T.-C. Huang. "AN-Coded Redundant Residue Number System for Reliable Neural Networks," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.
[18] C-S. Lin, J. Huang. P.-S. Chang, C.-Y. Tsai and T.-C. Huang. "SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.
[19] C.-D. Tsai, T.-Y. Chen, H.-W. Fu and T.-C. Huang. "TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network," 2021 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS2021), virtual, June 7, 2021.
[20] L.-Y. Lin, J. Schroff, T.-P. Lin and T.-C. Huang. "Residue Number System Design Automation for Neural Network Acceleration," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.
[21] W.-C. Yang, S.-Y. Lin and T.-C. Huang. "Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.
[22] L.-Y. Lin, J. Schroff, C.-C. Liang and T.-C. Huang. "Approximate Computing for Batch Learning in Neural Network," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.
[23] L.-Y. Lin, J. Schroff, T.-P. Lin and T.-C. Huang. Efficient Approximate Computing of Residue Number System for Neural Network Acceleration. TICD 2020 VLSI Design/CAD Symposium, Kaohsiung, Aug. 4-7, 2020.
[24] J. Huang, C.-S. Lin and T.-C. Huang. SAFER: Single Aging-Factor Enhanced Rings as Data Annotators and Early Warners of On-line Aging Monitoring for Automotive SoCs. TICD 2020 VLSI Design/CAD Symposium, Kaohsiung, Aug. 4-7, 2020.
[25] J. Huang and T.-C. Huang. Precompensation, BIST and Analogue Berger Codes for Reliable Neuromorphic RRAM. TICD the 14th VLSI Test Technology Workshop, Kaohsiung, July 27-29, 2020.
[26] J. Huang, C.-S. Lin and T.-C. Huang. SAFER: Single Aging-Factor-Enhanced Ring Oscillators for Aging Annotation and Early Warning for Co-Learning in On-Line Aging Monitors. TICD the 14th VLSI Test Technology Workshop, Kaohsiung, July 27-29, 2020.
[27] T.-C. Huang. Self-Checking Residue Number System for Low-Power Reliable Neural Network. Proceedings of The 28th IEEE Asian Test Symposium, pp.37-42, Kolkata, Dec 12,.2019.
[28] T.-C. Huang, C.-H. Chiang and M.-H.. Lin, "Low-Cost and Fast Design of Precise Activation Functions in Neural Network," 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Yilan, Taiwan, May 21, 2019.
[29] C.-H. Chiang, L.-Y. Lin, M.-H. Lin and T.-C. Huang. Accelerating Neural Network with Totally Self-Checking through Sigmoidal Activation Functions. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.
[30] W.-C. Yang and T.-C. Huang. Optimized Piecewise-Linear Lookup Table without Multipliers for Activation Functions in Neural Network. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.
[31] Y.-T. Chang, D.-Y. Wu, J. Huang, J.-C. Jhang and T.-C. Huang. Error-Resilient Neuromorphic RRAM. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.
[32] C.-H. Chiang, W.-C. Yang, L.-Y. Lin, M.-H. Lin and T.-C. Huang. Low-Power Compact Fast and Reliable Neural Network Based on Redundant Residue Number System. TICD the 13th VLSI Test Technology Workshop, Chiayi, July 2019.
[33] Yu-Teng Chang, Dong-Ying Wu, Jing Huang, Jia-Cheng Jhang and Tsung-Chu Huang. Two-Dimensional Analogue Berger Codes for Error-Resilient Neuromorphic RRAM. TICD the 13th VLSI Test Technology Workshop, Chiayi, July 2019.
[34] T.-C. Huang and J. Schroff (2018, Oct). Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. The 27th IEEE Asian Test Symposium, Hefei, pp.173-178, Oct. 2018.
[35] J. Schroff, D.-Y. Wu, J. Huang, Y.-R. Chen, W. Lee and T.-C. Huang. Linear-System-based Built-In Self-Test for Configurable Neuromorphic RRAM. 2018 VLSI Design/CAD Symposium, Tainan, Aug. 2018..
[36] Y.-T. Chang, J. Schroff, D.-Y. Wu, J. Huang and T.-C. Huang. Pre-degradation Compensation and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. 2018 VLSI Design/CAD Symposium, Tainan, Aug. 2018.
[37] C.-W. Lin and T.-C. Huang. Online defect tolerance scheme with CORDIC-based FFT of Dual Modular Redundancy application. 2018 the 12th VLSI Test Technology Workshop, Taichung, July 2018.
[38]D.-Y. Wu, J. Schroff, J. Huang, Y.-Ren Chen, W. Lee and T.-C. Huang. Compensation and BIST of Crossbar-based RRAM in Configurable Neural Network. 2018 the 12th VLSI Test Technology Workshop, Taichung, July 2018.
[39] Y.-S. Li, M.-J. Luo and T.-C. Huang. Multi-Cluster Error Correction for TSVs in 3D-ICs. 2018 the 12th VLSI Test Technology Workshop, Taichung, Jul. 2018.
[40] Y.-T. Chang, J. Schroff, D.-Y. Wu, J. Huang and T.-C. Huang. Precompensated Analogue Berger Codes for Self-Healing of Neuromorphic RRAM in Neural Network. 2018 the 12th VLSI Test Technology Workshop, Taichung, Jul. 2018.
[41] Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. 2017 VLSI Design / CAD Symposium, Pingtung, Aug. 2017.
[42] Y.-S. Li, S.-N. H. and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, Jul. 2017.
[43] Y.-S. Li, S.-N Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. TICD VLSI Design/CAD Symposium, Pingtung, Aug. 2017.
[44] Y.-C. Lin and T.-C. Huang. Multiple-TSV Schemes for Lagging-Defect Tolerant Clock-Delivery in 3D ICs. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.
[45] Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.
[46] T.-C. Huang and S.-Y. Huang. Doubling Schemes for Defect-Tolerant Clock-Delivery TSVs in Automotive 3D-ICs. IEEE ART joined with The 46th International Test Conference, Fort Worth, 2016.
[47] Y.-C. Lin and T.-C. Huang. A Multiple-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2017.
[48] Jhen-Sing Chen and T.-C. Huang. A Dual-Symptom Aging Monitor for Critical Data Interconnects. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2016.
[49] Kun-Yuan Li Mong-Lin Li Tsung-Chu Huang A Defect-Tolerant Multi-TSV Structure and Placement for Power-Grids in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug., 2016.
[50] Jhen-Sing Chen and T.-C. Huang. A Dual-Symptom Aging Monitor for Data-Delivery TSVs in 3D-ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.
[51] Y.-C. Lin and T.-C. Huang. A Double-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.
[52] Kun-Yuan Li, Mong-Lin Li and Tsung-Chu Huang. A Defect-Tolerant Structure and Placement for Power-Delivery TSVs in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.
[53] Bo-Shun Lin and Tsung-Chu Huang. A Precomputation-based Remapping Architecture for Hypercube-based Multi-dimensional Memory Repairing. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.
[54] Tsung-Chu Huang. ECMO: Error Clock-TSV Mending On-the-fly. IEEE The 45th International Test Conference, PO1.6, Anaheim, Oct. 6, 2015. (EI)
[55] Tsung-Chu Huang. Cluster Error Correction and On-Line Repair for Real-Time TSV Array. IEEE The 6th Asia Symposium on Quality Electronic Design, 3B-3, Kuala Lumpur, Aug. 5, 2015. (EI)
C) Patents
► Issued Patents
[1] Tsung-Chu Huang. 電路老化監測系統及其方法(Circuit Aging Monitor System and Method thereof). ROC Patent No.I768532, June 21, 2022.
[2] Tsung-Chu Huang. 矽穿孔自我繞線電路及其繞線方法(Through-Silicon Via Self-Routing Circuit and Routing Method thereof). ROC Patent No.I456706, Oct. 11, 2014.
[3] Tsung-Chu Huang. Through-silicon via self-routing circuit and routing method thereof. US Patent No.8,754,704, June 17, 2014.
[4] Tsung-Chu Huang. 記憶體位址重新映射裝置與修復方法(Memory Address Remapping Apparatus and Repairing Method thereof). ROC Patent No.I439857, June 1, 2014.
[5] Tsung-Chu Huang. 動態隨機存取記憶體之內容可定址記憶單元(DRAM-based Content Addressable Memory Cell). ROC Patent No.I440033, June 1, 2014.
[6] Tsung-Chu Huang. 大小比較器以及內含此比較器之內容可定址記憶體與不等寬色譜器(Magnitude Comparator, Magnitude Comparator Based Content Addressable Memory Cell, and Non-Equal Bin-Width Histogrammer). ROC Patent No.I409696, Sep. 21, 2013.
[7] Tsung-Chu Huang. Memory address remapping architecture and repairing method thereof. US Patent No.8,522,072, Aug. 27, 2013.
[8] Tsung-Chu Huang. 利用中央極限定理之常態分佈亂數產生器及其亂數產生方法(A Normal Distributed Random Number Generator by Using the CLT and the Random Number Generating Method thereof). ROC Patent No. I387921, Mar. 1, 2013. (NSC-94-2215-E-018-007-)
[9] Tsung-Chu Huang. 伯格反相碼之編解碼方法及其編碼器與檢查器電路(Berger Invert Code Encoding and Decoding Method). ROC Patent No. I377794, Nov. 21, 2012. (NSC-94-2215-E-018-007-)
[10] Tsung-Chu Huang. Magnitude comparator, magnitude comparator based content addressable memory cell, and non-equal bin width histogrammer. US Patent No.8,253,546, Aug. 28, 2012.(NSC-99-2221-E-018-025-)
[11] Tsung-Chu Huang. 低功率低面積全數位隨機抖動產生器(Low-Power Low-Area All-Digital Random Jitter Generator). ROC Patent No. I362833, Apr. 21, 2012. (NSC-94-2215-E-018-007-)