Publication

A) Journal Papers

[1] T.-C. Huang. Efficient and Dependable Approximate Computing of Residue Number System for Neural Network Acceleration. submitted to IEEE Design & Test. Nov. 4, 2020.

[2] Tsung-Chu Huang. Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. IEEE Communications Letters, vol.19, no.6, pp.917-920, Jun. 2015. [SCI, 2014 IF=1.463, TELECOMM](MOST-103-2221-E-018-032-)

[3] Tsung-Chu Huang. Cluster-Error Correction for Through-Silicon Vias in 3D ICs. IET Electronics Letters, vol. 51, no.3, pp.289-290, Feb. 2015.  [SCI, IF=1.068] (MOST-103-2221-E-018-032-)

[4] Yen-Chieh Huang and Tsung-Chu Huang. Dependable embedded memory for intelligent systems. Springer Verlag, Lecture Notes in Electrical Engineering, vol.234 LNEE, pp.573-579 , 2013. [EI, IF=0.13] (MOST-102-2221-018-030-)

[5] Tsung-Chu Huang. High-Performance Built-In Self-Routing for Through Silicon Vias. IET Electronics Letters, vol.48, no.9, pp.480-481, May 2012. (with invited feature, J. Baldwin. Routing for Moore, p.468) [SCI, 2011 IF=1.068, 131/245, EEE] (NSC-101-2221-E-018-036-)

[6] Tsung-Chu Huang. High-Yield Performance-Efficient Redundancy Analysis for 2D Memory. Science China: Information Science, 54(8):1663-1676 , Springer, Aug. 2011. [SCI, 2011 IF=0.644, 99/128, CS INFO SYS] (NSC-100-2221-E-018-014-)

[7] Tsung-Chu Huang. Multi-Valued Equal-Weight Codes for Self-Checking and Matching. IEEE Communications Letters, vol. 13, no. 12, pp.947-949, Dec. 2009. [SCI, 2009 IF=1.140, 23/77, TELECOMM] (NSC-99-2221-E-018-025-)

[8] Tsung-Chu Huang. A Low-Power Dependable Berger Code for Fully Asymmetric Communication. IEEE Communications Letters, vol. 12, no. 10, pp.773-775, Oct. 2008. [SCI, 2008 IF=1.232, 22/67, TELECOMM] (NSC-99-2221-E-018-025-)

[9] Wei-Yi He, Chen-An Chen and Tsung-Chu Huang. A Novel Random Access Scan for Reducing Peak Power, Test Data and Time. Chin-Yi Journal, ISSN 10219587, Vol. 25, pp.15-20, Dec. 2007.

[10] Tsung-Chu Huang. A Power Constrained Monitoring Scheme for SoC Testing. J. of Chongchou, vol. 18, pp.115-126, Feb. 2004. (NSC91-2215-E-235-001)

[11] Tsung-Chu Huang. A Low-Voltage Built-In Current Sensor Based on the Bulk-Driven Technique for Deep Submicron CMOS ICs. J. of Chongchou, Jul. 2003.

[12] Tsung-Chu Huang and Kuen-Jong Lee. A Hybrid LFSR Design for Low Power Applications. Journal of the Chinese Institute of Electrical Engineering, Vol.10, No.1, Pages 1-8, Jan. 2003. [EI, JCR04IF:0.208]

[13] Tsung-Chu Huang and Kuen-Jong Lee. An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits during Test Application. Journal of Electronic Testing – Theory and Applications, Vol.18, No.6, Pages 627-636, Dec. 2002. [EI, SCI, JCR04IF:0.480]

[14] Tsung-Chu Huang and Kuen-Jong Lee. Reduction of Power Consumption in Scan-based Circuits during Test Application by an Input Control Technique. IEEE Trans. on CAD of Circuits and Systems. 20(7): 911-917, July 2001. [EI, SCI, JCR04IF:0.913, Cited:2]

[15] Tsung-Chu Huang and Kuen-Jong Lee. Token Scan Cell for Low Power Testing. IEE Electronics Letter, 37(11): 678-679, May 2001. [EI, SCI, JCR04IF:0.968]

[16] Kuen-Jong Lee, Jing-Jou Tang, and Tsung-Chu Huang. BIFEST: A Built-in Intermediate Fault Effect Sensing and Test Generation System for CMOS Bridging Faults. ACM Trans. on Design Automation and Electronic System. 4(2): 194-218, Apr. 1999. [EI, SCI, JCR04IF:0.475]

B) Conference Papers

[1]  T. -Y. Chen, Z. -Y. Wang and T. -C. Huang, "TCB Convolution: Ternary-Coded Binarized Convolutions with Fixed-Point Filters," 2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), PingTung, Taiwan, 2023, pp. 95-96, doi: 10.1109/ICCE-Taiwan58799.2023.10226986.

[2]  C. Lin, H. Hsu and T. -C. Huang, "Redundant Lagrange Interpolation for Fault-Tolerant Winograd Convolution," 2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), PingTung, Taiwan, 2023, pp. 97-98, doi: 10.1109/ICCE-Taiwan58799.2023.10226694.

[3]  C.-D. Tsai, H.-W. Fu, T.-Y. Chen and T.-C. Huang. "TAIWAN Online: Test AI With AN Codes for Automotive Chips," IEEE 2021 International Test Conference -- Asia, Virtual (Shanghai), Aug. 18-20, 2021.

[4]  C.-D. Tsai, T.-Y. Chen, C.-Y. Tsai, P.-S. Chang and T.-C. Huang. "TCBNN: Ternary-Coded Binarized Neural Network with Per-Neuron Single-Arithmetic-Fault Tolerance," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.

[5]  C.-S. Lin, P.-S. Chang, C.-Y. Tsai and T.-C. Huang. "SAFER and SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for High-Correlation Early Warning in Online Aging Monitors of Automotive Chips," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.

[6]  H.-W. Fu, M.-W. Shen and T.-C. Huang. "AN-RNSNN: AN-Coded Redundant  Residue Number System for Neural Network Acceleration and Reliability," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.

[7]  T.-Y. Chen, C.-D. Tsai, H.-W. Fu, Y.-C. Yang and T.-C. Huang. "Error Correctable Range-Addressable Lookup for Any Activation Function of Neural Networks," TICD 2020 VLSI Design/CAD Symposium, Virtual (Kenting), Aug. 3-6, 2021.

[8]  C.-D. Tsai, T.-Y. Chen, C.-Y. Tsai, P.-S. Chang and T.-C. Huang. "Per-Neuron Single-Arithmetic-Fault Correctable Ternary-Coded Binarized Neural Network," TICD the 15th VLSI Test Technology Workshop, Virtual (Kaohsiung), July 19-20, 2021.

[9]  H.-W. Fu, M.-W. Shen and T.-C. Huang. "AN-Coded Redundant  Residue Number System for Neural Network Acceleration and Reliability," TICD the 15th VLSI Test Technology Workshop, Virtual (Kaohsiung), July 19-20, 2021.

[10]  T.-Y. Chen, C.-D Tsai, H.-W. Fu, Y.-C. Yang and T.-C. Huang. "Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.

[11]  H.-W. Fu, T.-Y. Chen, C.-D. Tsai, M.-W. Shen and T.-C. Huang. "AN-Coded Redundant  Residue Number System for Reliable Neural Networks," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.

[12]  C-S. Lin, J. Huang. P.-S. Chang, C.-Y. Tsai and T.-C. Huang. "SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs," 2021 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Penghu, Taiwan, June 17, 2021.

[13]  C.-D. Tsai, T.-Y. Chen, H.-W. Fu and T.-C. Huang. "TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network," 2021 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS2021), virtual, June 7, 2021.

[14]  L.-Y. Lin, J. Schroff, T.-P. Lin and T.-C. Huang. "Residue Number System Design Automation for Neural Network Acceleration," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.

[15]  W.-C. Yang, S.-Y. Lin and T.-C. Huang. "Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.

[16]  L.-Y. Lin, J. Schroff, C.-C. Liang and T.-C. Huang. "Approximate Computing for Batch Learning in Neural Network," 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Taoyuan, Taiwan, Sep. 29, 2020.

[17]  L.-Y. Lin, J. Schroff, T.-P. Lin and T.-C. Huang. Efficient Approximate Computing of Residue Number System for Neural Network Acceleration. TICD 2020 VLSI Design/CAD Symposium, Kaohsiung, Aug. 4-7, 2020.

[18]  J. Huang, C.-S. Lin and T.-C. Huang. SAFER: Single Aging-Factor Enhanced Rings as Data Annotators and Early Warners of On-line Aging Monitoring for Automotive SoCs. TICD 2020 VLSI Design/CAD Symposium, Kaohsiung, Aug. 4-7, 2020.

[19] J. Huang and T.-C. Huang. Precompensation, BIST and Analogue Berger Codes for Reliable Neuromorphic RRAM. TICD the 14th VLSI Test Technology Workshop, Kaohsiung, July 27-29, 2020.

[20] J. Huang, C.-S. Lin and T.-C. Huang. SAFER: Single Aging-Factor-Enhanced Ring Oscillators for Aging Annotation and Early Warning  for Co-Learning in On-Line Aging Monitors. TICD the 14th VLSI Test Technology Workshop, Kaohsiung, July 27-29, 2020.

[21] T.-C. Huang. Self-Checking Residue Number System for Low-Power Reliable Neural Network. Proceedings of The 28th IEEE Asian Test Symposium, pp.37-42, Kolkata, Dec 12,.2019.

[22] T.-C. Huang, C.-H. Chiang and M.-H.. Lin, "Low-Cost and Fast Design of Precise Activation Functions in Neural Network," 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), Yilan, Taiwan, May 21, 2019.

[23]  C.-H. Chiang, L.-Y. Lin, M.-H. Lin and T.-C. Huang. Accelerating Neural Network with Totally Self-Checking through Sigmoidal Activation Functions. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.

[24]  W.-C. Yang and T.-C. Huang. Optimized Piecewise-Linear Lookup Table without Multipliers for Activation Functions in Neural Network. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.

[25]  Y.-T. Chang, D.-Y. Wu, J. Huang, J.-C. Jhang and T.-C. Huang. Error-Resilient Neuromorphic RRAM. TICD 2019 VLSI Design/CAD Symposium, Kaohsiung, Aug. 2019.

[26]  C.-H. Chiang, W.-C. Yang, L.-Y. Lin, M.-H. Lin and T.-C. Huang. Low-Power Compact Fast and Reliable Neural Network Based on Redundant Residue Number System. TICD the 13th VLSI Test Technology Workshop, Chiayi, July 2019.

[27]  Yu-Teng Chang, Dong-Ying Wu, Jing Huang, Jia-Cheng Jhang and Tsung-Chu Huang. Two-Dimensional Analogue Berger Codes for Error-Resilient Neuromorphic RRAM. TICD the 13th VLSI Test Technology Workshop, Chiayi, July 2019.

[28]  T.-C. Huang and J. Schroff (2018, Oct). Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. The 27th IEEE Asian Test Symposium, Hefei, pp.173-178, Oct. 2018.

[29]  J. Schroff, D.-Y. Wu, J. Huang, Y.-R. Chen, W. Lee and T.-C. Huang. Linear-System-based Built-In Self-Test for Configurable Neuromorphic RRAM. 2018 VLSI Design/CAD Symposium, Tainan, Aug. 2018..

[30]  Y.-T. Chang, J. Schroff, D.-Y. Wu, J. Huang and T.-C. Huang. Pre-degradation Compensation and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. 2018 VLSI Design/CAD Symposium, Tainan, Aug. 2018.

[31] C.-W. Lin and T.-C. Huang. Online defect tolerance scheme with CORDIC-based FFT of Dual Modular Redundancy application. 2018 the 12th VLSI Test Technology Workshop, Taichung, July 2018.

[32]D.-Y. Wu, J. Schroff, J. Huang, Y.-Ren Chen, W. Lee and T.-C. Huang. Compensation and BIST of Crossbar-based RRAM in Configurable Neural Network. 2018 the 12th VLSI Test Technology Workshop, Taichung, July 2018.

[33]   Y.-S. Li, M.-J. Luo and T.-C. Huang. Multi-Cluster Error Correction for TSVs in 3D-ICs. 2018 the 12th VLSI Test Technology Workshop, Taichung, Jul. 2018.

[34]   Y.-T. Chang, J. Schroff, D.-Y. Wu, J. Huang and T.-C. Huang. Precompensated Analogue Berger Codes for Self-Healing of Neuromorphic RRAM in Neural Network. 2018 the 12th VLSI Test Technology Workshop, Taichung, Jul. 2018.

[35]   Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. 2017 VLSI Design / CAD Symposium, Pingtung, Aug. 2017.

[36] Y.-S. Li, S.-N. H. and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, Jul. 2017.

[37] Y.-S. Li, S.-N Huang and T.-C. Huang. Low-Latency Multiple Cluster Error Correction for TSV Arrays in 3D-ICs. TICD VLSI Design/CAD Symposium, Pingtung, Aug. 2017.

[38] Y.-C. Lin and T.-C. Huang. Multiple-TSV Schemes for Lagging-Defect Tolerant Clock-Delivery in 3D ICs. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.

[39] Y.-S. Li, S.-N. Huang and T.-C. Huang. Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays. TICD the 11th VLSI Test Technology Workshop, Nantou, July 11, 2017.

[40] T.-C. Huang and S.-Y. Huang. Doubling Schemes for Defect-Tolerant Clock-Delivery TSVs in Automotive 3D-ICs. IEEE ART joined with The 46th International Test Conference, Fort Worth, 2016.

[41] Y.-C. Lin and T.-C. Huang. A Multiple-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2017.

[42] Jhen-Sing Chen and T.-C. Huang. A Dual-Symptom Aging Monitor for Critical Data Interconnects. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug. 1, 2016.

[43] Kun-Yuan Li Mong-Lin Li Tsung-Chu Huang A Defect-Tolerant Multi-TSV Structure and Placement for Power-Grids in 3D ICs. TICD VLSI Design/CAD Symposium, Kaohsiung, Aug., 2016.

[44] Jhen-Sing Chen and T.-C. Huang. A Dual-Symptom Aging Monitor for Data-Delivery TSVs in 3D-ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[45] Y.-C. Lin and T.-C. Huang. A Double-TSV Scheme for Defect-Tolerant Clock-Delivery in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[46] Kun-Yuan Li, Mong-Lin Li and Tsung-Chu Huang. A Defect-Tolerant Structure and Placement for Power-Delivery TSVs in 3D ICs. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[47] Bo-Shun Lin and Tsung-Chu Huang. A Precomputation-based Remapping Architecture for Hypercube-based Multi-dimensional Memory Repairing. TICD the 10th VLSI Test Technology Workshop, Nantou, July, 2016.

[48]  Tsung-Chu Huang. ECMO: Error Clock-TSV Mending On-the-fly. IEEE The 45th International Test Conference, PO1.6, Anaheim, Oct. 6, 2015. (EI)

[49]  Tsung-Chu Huang. Cluster Error Correction and On-Line Repair for Real-Time TSV Array. IEEE The 6th Asia Symposium on Quality Electronic Design, 3B-3, Kuala Lumpur, Aug. 5, 2015. (EI)

[50] Yi-Sheng Lin, Lung-Yun Chang and Tsung-Chu Huang. Zero-Latency Cluster-Error Correction for TSVs in 3D ICs.  TICD VLSI Design and CAD Symposium, Hualian, Aug. 4, 2015.

[51] Yi-Sheng Lin, Lung-Yun Chang, Yu-Jen Li and Tsung-Chu Huang. Zero-Latency Cluster-Error Correction for TSV Arrays in Stacked Memory. The 9th VLSI Test Technology Workshop, 4-1, Tainan, July 14, 2015.

[52] Wei-Ting Liu and Tsung-Chu Huang. An On-Line Monitoring and Repairing Architecture for Clock TSVs in 3D-ICs. The 9th VLSI Test Technology Workshop, 4-4, Tainan, July 14, 2015.

[53] Tsung-Chu Huang and Yu-Yi Chen. Low-Latency Error-Correction Decoding for Clustered TSVs. TICD VLSI Design and CAD Symposium, P2, Taichung, Aug. 2014.

[54]   Hsuan-Yu Fu, Sheng-An Lu, and Tsung-Chu Huang. An Iterative Logic Array for Selecting TSVs in 3D ICs. TICD VLSI Design and CAD Symposium, S07-09, Taichung, Aug. 2014.

[55]   Hsuan-Yu Fu, Sheng-An Lu, and Tsung-Chu Huang. Multi-way Built-In Self-Router for 3D ICs. Workshop on Consumer Electronics, Nov. 2014.

[56] Yen-Chieh Huang and Tsung-Chu Huang. Dependable Embedded Memory for Intelligent Systems. Proc. in International Conference on Intelligent Technologies and Engineering Systems, B5-1, Changhua, Taiwan, Dec. 13-15. 2012.

[57] Sheng-An Lu, Yi-Jing Wu and Tsung-Chu Huang. Dependable Inter-Chip Communications via Built-In Self-Routers. In Proc. 2012 National Symposium on Telecommunications, B2-5, Changhua, Nov. 16, 2012.

[58] Sheng-An Lu Yi-Jing Wu Tsung-Chu Huang. Built-In Self-Routers for Repairing TSVs in 3D ICs. In Proc. the 6th VLSI Test Technology Workshop, Yilan, July 10, 2012.

[59] Kuei-Yeh Lu, Yen-Chieh Huang, Jian-Ci Wang and Tsung-Chu Huang. EXTREMES: External Repair for Clustered Faults of Memory to the Extremes. In Proc.of the 5th VLSI Test Technology Workshop, pp.89-94, Nantao, July 15, 2011.

[60] Yun-Ping Wang and Tsung-Chu Huang. Magnitude-Comparator-Based CAM for Efficient Hybrid Routers. In Proc. Electronic Technology Symposium, Kaohsiung, EO-01, June 10, 2011. (NSC-99-2221-E-018-025-)

[61] Yu-Ching Wen and Tsung-Chu Huang. Searching-Once Single-Transistor MLC Flash CAM. In Proc. of the 6th Intelligent Living Technology Conference, ISBN.987-957-21-8031-0, pp.975-980, June 5, 2011. (NSC-99-2221-E-018-025-)

[62] Yu-Ting Lin and Tsung-Chu Huang. A Low-Cost High-Speed Constant-Weight Code Checker. In Proc. Conf. on Electronic Communication and Applications, pp.480-485, Kaohsiung, May 20, 2011. (NSC-99-2221-E-018-025-)

[63] T.-C. Huang, K.-Y. Lu and Y.-C. Huang. HYPERA: High-Yield Performance-Efficient Redundancy Analysis. In Proc. IEEE 19th Asian Test Symposium, pp.231-235 Shanghai, Dec. 1-4, 2010.[EI](NSC-99-2221-E-018-025-)

[64] Kwei-Yeh Lu, Yen-Chieh Huang and Tsung-Chu Huang. A High-Yield Architecture for Memory Repairing. In Proc.2010 Workshop on Consumer Electronics, pp.835-842, Tainan, Nov. 5, 2010.

[65] Yun-Ping Wang and Tsung-Chu Huang. Comparator-Based Content-Addressable Memory and Application for a Novel IP Router. In Proc.2010 Workshop on Consumer Electronics, pp.79-86, Tainan, Nov. 5, 2010.

[66] Yu-Ching Wen and Tsung-Chu Huang. Low-Cost Fast MLC Flash CAM. In Proc.2010 Workshop on Consumer Electronics, pp.62-70, Tainan, Nov. 5, 2010.

[67]  Pin-Chung Chen, Sheng-Jie Fan, Yun-Ping Wang, Yung-Sheng Kao and Tsung-Chu Huang. Area-Efficient High Goodness-of-Fit Noise Generator for Communication Test. The 4th VLSI Test Technology Workshop, S3-2, Yilan, Aug. 19, 2010.

[68] Wei-Ning Hsu, Yu-Ching Wen and Tsung-Chu Huang. Dependable and Area-Efficient Equal-Weight Coded Content-Addressable Memory. The 21th VLSI Design and CAD Symposium, pp.135-138, Kaohsiung, Taiwan, Aug. 5, 2010. 

[69] Pin-Chong Chen, Sheng-Jie Fan, Tsung-Chu Huang. Distribution-Compensable Random-Number Generator for High-Goodness-of-Fit Jitter Generator. In Proc. 2010 Electronic Technology Symposium, Session BO-05, Kaohsiung, June 18, 2010.

[70] Sheng-Jie Fan, Pin-Chong Chen and Tsung-Chu Huang. Distribution-Compensable Jitter Generator for Bit-Error-Rate Test. In Proc. of the 4th Conf. on Integrated Opto-Mechatronic Technology and Intellectual Property Rights, pp.87-96, Taipei, May 12, 2010.

[71] Wei-Ning Hsu, Tsu-Hsin Wu and Tsung-Chu Huang. Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency. IEEE International Workshop on Memory Technology, Design and Testing, Hsinchu, pp.38-41, Aug. 31, 2009.

[72] Yi-Hsien Chou, Tsu-Hsin Wu, Pin-Chung Chen and Tsung-Chu Huang. Distribution-Compensable Jitter Generator for Communication Test. The 20th VLSI Design and CAD Symposium, Hualian, Taiwan, pp.574-577, Aug. 5, 2009.

[73] Yi-Hsien Chou, Tsu-Hsin Wu and Tsung-Chu Huang. Low-Cost CLT-based Random Number Generator for Communication Test. The 3rd VLSI Test Technology Workshop, pp.79-82, Nantao, July 16, 2009.

[74] Yi-Hsian Chou, Sheng-Jie Fen, Tsu-Hsin Wu and Tsung-Chu Huang. Low-Cost Fast Distribution-Programmable Jitter Generators for Communication Test. In Proc. of the 4th Intelligent Living Technology Conference, ISBN.987-957-21-7031-1, pp.837-843, June 5, 2009.

[75] Choa-Nan Liu, Shih-Chuan Lo and Tsung-Chu Huang. Inverting Techniques for Low-Power Dependable Fully-Asymmetric Communication and Storage Systems. In Proc. of the 4th Intelligent Living Technology Conference, ISBN.987-957-21-7031-1, pp.896-901, June 5, 2009. 

[76] Hsiao-Han Hou, Yi-Hsien Chou and Tsung-Chu Huang. A Low-Cost and Fast Normal-Distribution Random Number Generator. PAL Consortium Conference on Innovation Applications of System Prototyping and Circuit Design, pp.130-134, Oct. 17, 2008.

[77] Choa-Nan Liu, Shun-Dao Lin and Tsung-Chu Huang. Berger Inver Codes: A Low-Power Dependable Code for Fully Asymmetric Communication. PAL Consortium Conference on Innovation Applications of System Prototyping and Circuit Design, pp.336-340, Oct. 17, 2008.

[78] Cheng-Han Yang, Yi-Hsian Chou and Tsung-Chu Huang. Area-Efficient True One-Period Delayline for Cycle-to-Cycle Jitter Measurement. The 19th VLSI Design/CAD Symposium, Hualian, Taiwan, pp.280-283, 7 Aug. 2008.

[79] Chih-Jong Chen and Tsung-Chu Huang. MTCMOS SRAM Design for Data-Retention and High-Resolution Current Test. The 2nd VLSI Test Technology Workshop, pp.20-25, Tainan, July 17, 2008.

[80]  Cheng-Han Yang, Yi-Hsian Chou, and Tsung-Chu Huang. Area-Efficient True One-Period Delay Jitter Measurement. The 2nd VLSI Test Technology Workshop, pp.83-86, Tainan, July 18, 2008.

[81]  Hsin-Ling Chen, Ling Li, Choa-Nan Liu, and Tsung-Chu Huang. A Novel Adaptive-Data-Retention CMOS Logic Structure for IDDS Test. The 2nd VLSI Test Technology Workshop, pp.109-114, Tainan, July 18, 2008.

[82]  Hsin-Ling Chen, and Tsung-Chu Huang. Low-Power High-Speed High-Current-Testability Cell-Based Design Automation. The 16th National Conference on Automation Technology, pp. 1189-1195, Kaohsiung, June 27, 2008.

[83] Cheng-Han Yang, Yi-Hsien Chou, and Tsung-Chu Huang. Area-Efficient Double-Period-Delay Jitter Measurement. 2008 Microelectronics Technology and Applications, pp.395-400, Kaohsiung, May. 16, 2008.

[84] Yuan-Wei Chao, Hsin-Ling Chen, Chih-Jong Chen and Tsung-Chu Huang. Power-Gating Current Test for Static RAM in Nanotechnologies. IEEE International Workshop on Memory Technology, Design and Testing, pp.42-45, Taipei, Dec. 3, 2007.

[85] Yuan-Wei Chao adn Tsung-Chu Huang. Design for Fast and High-Resolution Current Testability of SRAM in Nanotechnology. IEEE Workshop on Consumer Electronics and Signal Processing, pp.545-549, Taichung, Taiwan, Nov. 2, 2007.

[86] Chen-An Chen, Wei-Yi He and Tsung-Chu Huang. A Single-Clock Enhanced Random Access Scan. The 18th VLSI Design/CAD Symposium, pages 21-24, Hualian, Taiwan, 7 Aug. 2007.

[87] Wei-Yi He, Chen-An Chen and Tsung-Chu Huang. A Novel Random Access Scan for Reducing Peak Power, Test Data and Time. IEEE Intelligent Living Technology, pp.623-628, Taichung, Taiwan, June 1, 2007.

[88] Tsung-Chu Huang, Gau-Bin Chang and Ling Li. Congruence Synchronous Mirror Delay. In Proc. IEEE Int'l Symp. on Circuits and Systems, pp.2184-2187, New Orleans, May 27-30, 2007. [EI](NSC95-2221-E-018-023-)

[89] Tsung-Chu Huang and Ling Li. IDDS Testing: A High-Resolution Current Test Scheme for Nanotechnologies. IEEE International Workshop on Current and Defect Based Test in conjunction with ITC, pp.25-28, Santa Clara, Oct. 27, 2006.(NSC95-2221-E-018-023-)(Partly, ITRI/STC:S3-S94-S02)

[90] Tsung-Chu Huang, Ling Li and Yuan-Wei Chao. IDDS Testing for Nanotechnologies. The 17th VLSI Design/CAD Symposium, pages 707-710, Hualian, Taiwan, 11 Aug. 2006.(NSC95-2221-E-018-023-)

[91] Tsung-Chu Huang, Jing-Chi Tzeng, Yuan-Wei Chao, Ji-Jan Chen, Wei-Ting Liu and Kuen-Jong Lee. A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling. In Proc. IEEE VLSI Design,Automation and Test, pages 167-170, Apr. 27, 2006. (NSC93-2215-E-018-004-)

[92] Jing-Chi Tzeng and Tsung-Chu Huang. Vector Control Technique and Sleep-Transistor Allocation for Supply-Gating Current Spike Reduction in Power Management. In Proc. IEE Mobility Conference, Session 3-2A2, Guangzhou, China, 15 Nov. 2005. [EI] (NSC93-2215-E-018-004-)

[93] Gau-Bin Chang, Jing-Chi Tzeng and Tsung-Chu Huang. A Low-Area Digital Synchronous Mirror Delay. The 16th VLSI Design/CAD Symposium, Session P1, Hualian, Taiwan, 10 Aug. 2005. (NSC94-2215-E-018-007-)

[94] Tsung-Chu Huang and Chang-Chin Yeh. A Hybrid Scheme of BIST Scheduling and Monitoring for Thermal and Power Constrained Concurrent SoC Test. The 14th VLSI Design/CAD Symposium, P4-17, Hualian, Taiwan, Aug. 2003. (NSC91-2215-E-235-001)

[95] Tsung-Chu Huang and Kuen-Jong Lee. A Low-Power LFSR Architecture. The Tenth Asian Test Symposium, Kyoto, Japan, Nov. 19, 2001. [EI]

[96] Tsung-Chu Huang and Kuen-Jong Lee. A Token Scan Architecture for Low Power Testing. Proc. IEEE International Test Conference, Session 24-2, Baltimore, Maryland, US, Oct. 30, 2001. [EI]

[97] Kuen-Jong Lee, Jih-Jeen Chen and Tsung-Chu Huang. Test Power Reduction for Scan-Based Design. The 12th VLSI Design/CAD Symposium, Session A3-10, Hsinchu, Taiwan, 14 Aug. 2001.

[98] Tsung-Chu Huang and Kuen-Jong Lee. A Token Structure for Low Power Scan Design. The 12th VLSI Design/CAD Symposium, Session A3-1, Hsinchu, Taiwan, 14 Aug. 2001.

[99] Kuen-Jong Lee, Tsung-Chu Huang, and Jih-Jeen Chen. Peak-Power Reduction for Multiple-Scan Circuits during Test Application. The Ninth Asian Test Symposium, pages 453-458, Taipei, Taiwan, Dec. 4, 2000. [EI]

[100]Tsung-Chu Huang and Kuen-Jong Lee. Interleaving Multiple Scan Technique to Reduce Peak-Power. The 11th VLSI Design/CAD Symposium, pages 385-388, Pintung, Taiwan, Aug. 2000.

[101]Tsung-Chu Huang and Kuen-Jong Lee. An Input Control Technique for Power Reduction in Scan Circuits During Test Application. The Eighth Asian Test Symposium, pages 315-320, Singapore, Nov. 16, 1999. [EI]

[102]Tsung-Chu Huang and Kuen-Jong Lee. Test Power Reduction During Scan Operation Via Input Control. The 10th VLSI Design/CAD Symposium, pages 107--110, Touyuan, Taiwan,  Aug. 18, 1999.

[103]Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh, and Tsung-Chu Huang. On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. The 9th VLSI Design/CAD Symposium, pages 177-180, Nantou, Taiwan, Aug. 19, 1998.

[104]Tsung-Chu Huang and Kuen-Jong Lee. A New Built-in Current Sensor for Deep Submicron CMOS ICs. The 9th VLSI Design/CAD Symposium, pages 141-144, Nantou, Taiwan, Aug. 19, 1998.

[105]Tsung-Chu Huang and Kuen-Jong Lee. Bulk-Driven Technique for Current Testing. Int'l Conf. on Chip Technology, pages 158-165, Hsinchu, Taiwan, Apr. 1998.

[106]Tsung-Chu Huang, Kuen-Jong Lee, and Min-Cheng Huang. Built-In Current Sensor Designs Based on the Bulk-driven Technique. The Sixth Asian Test Symposium, pages 384-389, Akita, Japan, Nov. 1997. [EI]

[107]Tsung-Chu Huang, Kuen-Jong Lee, and Min-Cheng Huang. A High-Speed Low-Voltage Built-In Current Sensor. IEEE workshop on IDDQ Testing, pages 90-94, Washington D.C., US, Nov. 1997. [EI]

[108]Kuen-Jong Lee, Tsung-Chu Huang, and Min-Cheng Huang. A Log-Voltage Built-In Current Sensing Technique. The 8th VLSI Design/CAD Symposium, pages 51-54, Chiai, Taiwan, Aug. 1997.

[109]Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, and Cheng-Liang Tsai. Combination of Automatic Test Pattern Generation and Built-In Intermediate Voltage Sensing for Detecting CMOS Bridging Faults. The Fifth Asian Test Symposium, pages 100-105, Hsinchu, Taiwan, Nov. 1996. [EI]

[110]Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, and Cheng-Liang Tsai. Detecting Bridging Faults using Logic Testing Only. The 7th VLSI Design/CAD Symposium, pages 73-76, Nantou, Taiwan, Aug. 1996.

C) Patents

        ► Issued Patents

[1] Tsung-Chu Huang. 矽穿孔自我繞線電路及其繞線方法(Through-Silicon Via Self-Routing Circuit and Routing Method thereof). ROC Patent No.I456706, Oct. 11, 2014.

[2] Tsung-Chu Huang. Through-silicon via self-routing circuit and routing method thereof. US Patent No.8,754,704, June 17, 2014.

[3] Tsung-Chu Huang. 記憶體位址重新映射裝置與修復方法(Memory Address Remapping Apparatus and Repairing Method thereof). ROC Patent No.I439857, June 1, 2014.

[4] Tsung-Chu Huang. 動態隨機存取記憶體之內容可定址記憶單元(DRAM-based Content Addressable Memory Cell). ROC Patent No.I440033, June 1, 2014.

[5] Tsung-Chu Huang. 大小比較器以及內含此比較器之內容可定址記憶體與不等寬色譜器(Magnitude Comparator, Magnitude Comparator Based Content Addressable Memory Cell, and Non-Equal Bin-Width Histogrammer). ROC Patent No.I409696, Sep. 21, 2013.

[6] Tsung-Chu Huang. Memory address remapping architecture and repairing method thereof. US Patent No.8,522,072, Aug. 27, 2013.

[7] Tsung-Chu Huang. 利用中央極限定理之常態分佈亂數產生器及其亂數產生方法(A Normal Distributed Random Number Generator by Using the CLT and the Random Number Generating Method thereof). ROC Patent No. I387921, Mar. 1, 2013. (NSC-94-2215-E-018-007-)

[8] Tsung-Chu Huang. 伯格反相碼之編解碼方法及其編碼器與檢查器電路(Berger Invert Code Encoding and Decoding Method). ROC Patent No. I377794, Nov. 21, 2012. (NSC-94-2215-E-018-007-)

[9] Tsung-Chu Huang. Magnitude comparator, magnitude comparator based content addressable memory cell, and non-equal bin width histogrammer. US Patent No.8,253,546, Aug. 28, 2012.(NSC-99-2221-E-018-025-)

[10] Tsung-Chu Huang. 低功率低面積全數位隨機抖動產生器(Low-Power Low-Area All-Digital Random Jitter Generator). ROC Patent No. I362833, Apr. 21, 2012. (NSC-94-2215-E-018-007-)

        ► Patents under Pending

[1] Tsung-Chu Huang. 電路老化監測系統及其方法(Circuit Aging Monitor System and Method thereof). ROC Patent, under pending, App. No.109138488 , Nov. 4, 2020.

D) Books & Technical Reports

[1] 黃宗柱編著，“資料結構 – 使用C語言”，第三波出版社，Jul. 1989。

[2] 唐經洲、黃宗柱編著，“微處理機導論”，ISBN: 957-21-1471-9，全華出版社，Jul. 1996。

(publication in 5 years)