Syllabus
Google Meet: https://meet.google.com/hrw-pnmg-iea
Course Title: VLSI Design (International Engineering Master Degree Program & EMI)
Course No. 55002
Semester: Fall, 2023
Time and Classroom: Fri. 09:05-12:00 (E406, x8331)
Credits: 3
Lector: Professor Tsung-Chu Huang
Email: tch@cc.ncue.edu.tw
Tel. (04)7232105 ext. 8384
Website: http://testlab.ncue.edu.tw/tch
NCUE dLearn Cloud: https://dlearn.ncue.edu.tw (MOOCS)
Textbook and References
Textbook:
Neil H. E. Weste and David Harris. "CMOS VLSI Design -- A Circuits and Systems Perspective." 3rd Ed., Addison Wesley, 2005. (Agency: Wei-Ming, ISBN:0201533766 http://www.wmbook.com.tw) Lecture website: http://www.cmosvlsi.com. (google for VLSI + textbook)
Reference:
Sung-Mo Kang & Yusuf Leblebigi. "CMOS Digital Integrated Circuits -- Analysis and Design." 2nd Ed., Mc Graw Hill. (Agency: Chwa)
John P. Uyemura. "Introduction to VLSI Circuits and Systems." John Wiley & Sons. 2002. (Agency: Chwa)
Lectures released from the CIC and the Digital Intellectual Property Consortium, Taiwan.
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Schedule and Contents
Week 2 3/03 Basic Devices (RCLT) and Transistor Theory [PDF, PPT]
Week 3 3/10 SPICE Model and Tool [PDF, PPT] (Lab) (SNM Example: SNM.sp, SNM.m)
Week 4 3/17 Labs of HSPICE (1)
Week 5 3/24 Labs of HSPICE (2)
Week 6 3/31 (Spring Vacation: 3/30-4/05)
Week 7 4/07 Introduction to Virtuoso Layout [PPTtemp] (https://www.youtube.com/channel/UCy4Xb0-8aApH0DltCbqkAYg) and SKILL [PPT]
Week 8 4/14 CMOS Gates and SNMs [PDF, PPT, HW2), Labs of Full Custom Layout,
Week 9 4/21 Midterm exam [HW1]
Week 10 4/28 Linear Models for Element Sizing, Matched Layout and Power Dissipation [PDF, PPT] (Excise Verilog Coding, refer to videos VeriloggerPro and ModelSimAE
Week 11 5/05 Simple OPAMP Design [PDF, PPT]IO Pads, [PDF, PPT]
Week 13 5/19 Cell-based Design and Design Flow
Week 14 5/26 ALU/Datapath Design [PPT]
Week 16 6/09 Introduction to Digital IC Testing [PDF, PPT] (Memory [PDF, PPT], Array [PPT] and Memory Test)
Week 17 6/16 Finals
Week 18 6/23 (Dragon Boat Festival) Final exam, Discussion, Project due, Introduction to Datapath (1/11)
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Criteria
Participation: 10%
Midterm Exam: 30%
Final Exam: 30%
Term Project:30% (Download Template here) (Note: including schematic, pre-sim, layout and post-sim)
Supplement Links
No. |
Title |
URL |
Remark |
1 |
Semiconductor Technology |
Semiconductor Technology at TSMC, 2011 |
|
2 |
FinFET
Process |
Understanding The FinFet Semiconductor Process |
|
3 |
FinFET
Chip Fabrication |
Intel 22nm
FinFET Chip Fabrication Process |
|
4 |
Sand to
Silicon |
GLOBALFOUNDRIES Sand to Silicon |
|
5 |
3D-IC
Stacking Process |
3D
Integration Animation - EPFL |
|
6 |
3D-IC
Stacking Process |
Fraunhofer
3D Integration |
|
7 |
TSV
Process |
SigmaTech
TSV Video.mov |
|
8 |
MOSFET
Process |
How MOSFETs
and Field-Effect Transistors Work! |
A variety of On-Line VLSI/CAD Websites:
1. Coding Ground: Compiling in the Heaven (Cloud) ! http://www.tutorialspoint.com/codingground.htm
2. PartSim: Online Schematics Simulator (http://www.partsim.com)
3. NGSPICE: Online Spice Simulator (http://www.ngspice.com)
4. iVerilog: Verilog Online (http://iverilog.com)
5. Magic VLSI: (Online) Cell-based Synthesizer / Layout (http://opencircuitdesign.com/magic)
6. Debian Linux Package Download: https://www.debian.org/CD/http-ftp/
7. Debian Linux Package Installation: https://www.youtube.com/results?search_query=debian+%E5%AE%89%E8%A3%9D
8. Cadence II Virtuoso Installation and Tutorials: https://www.youtube.com/results?search_query=virtuoso+layout+%E6%95%99%E5%AD%B8