|
姓名
|
Name
|
級別
|
Research (研究方向)
|
Company |
|
張高賓
|
Gau-Bin Chang
|
MS06
|
Congruence Synchronous Mirror Delay and its Built-In Self Test
|
Chimei(奇美)
|
|
曾景祺
|
Jing-Chi Tzeng
|
MS06
|
Data Retention and Spike Reduction
for Supply Gating Power Management in Nanometer Technology
|
SpringSoft
(思源)
|
|
何威毅
|
Wei-Yi He
|
MS07
|
A Random Access Scan with Combinational Output Observable Logics
|
台東監獄
公務員
|
|
李菱
|
Ling Li
|
MS07
|
Adaptive Data-Retention Cell Design for High-Resolution Current Testability
|
CPT
(昭威科技)
|
|
趙元偉
|
Yuan-Wei Chao
|
MS07
|
Design for Fast and High-Resolution Current Testability of SRAM in Nanotechnology
|
勝品電通
|
|
陳振岸
|
Chen-An Chen
|
MS08
|
A Single-Clock Enhanced Random Access Scan |
ITRI
(工研院資通所)
|
|
楊承翰
|
Cheng-Han Yang
|
MS08
|
Area-Efficient Double-Period-Delay Jitter Measurement
|
Pegatron
(和碩科技)
|
|
陳欣伶
|
Hsin-Ling Chen
|
MS08
|
Area-Efficient Adaptive Data-Retention Logics Simultaneously for Spike Reduction and IDDS Testability
|
Chroma
(致茂電子)
|
| 劉昭男 |
Choa-Nan Liu |
MS09
|
Coding Design for Dependability and Reliability |
AllPilot
(全航科技)
|
| 周益賢 |
Yi-Hsien Chou |
MS09
|
Low-Power Area-Efficient Jitter Generator/Measurement |
朋億科技
(Novatech)
|
| 林偉靖 |
W.-J. Lin |
MIS08 |
Reliability Analysis on Probe Cards |
SPIL
(矽品)
|
| 范勝杰 |
Sheng-Jie Fan |
MS10
|
Distribution-Compensable Jitter Generators |
竹科
PCB Test
|
| 許韋寧 |
Wei-Ning Hsu
|
MS10
|
Binary Content Addressable Memory |
Lyontek
(來揚科技)
|
| 陳品充 |
Pin-Chong Chen |
MS10 |
Random Number Generators for Distribution Compensable Noise/Jitter Generation |
服役中
|
| 王雲平 |
Yun-Ping Wang |
MS11
|
Magnitude-Comparator-Based CAM |
Etron
(鈺創科技)
|
| 溫又卿 |
Yu-Ching Wen |
MS11
|
Flash Memory Based CAM |
Giantplus
(凌巨科技)
|
| 林毓庭 |
Yu-Ting Lin |
MS11 |
Constant-Weight Codes for CAM Desogn |
-
|
| 陸貴葉 |
Kwei-Yeh Lu |
MS11 |
CAM-Based Memory BISR |
Chimei
(奇美統寶光電)
|
| 鄭時昇 |
Shih-Sheng Cheng |
MS12 |
Universal Remapping Architectures for Redundant Repairing |
友達光電
(AUO)
|
| 呂勝安 |
Sheng-An Lu |
MS13 |
Address Configuration for 3D Memory Array |
聯陽半導體
(ITE) |
| 高泳生 |
Yung-Sheng Kao |
MS13 |
Comparator-based CAM for RNG Table Minimization |
|
| 黃彥傑 |
Yen-Chieh Huang |
MS13 |
High-Yield Built-In Self-Repair for HMCs |
聯聖企管 |
| 傅絢鈺 |
Hsuan-Yu Fu |
MS14 |
Multi-Way Built-In Self-Routers for Interposers in 3D-ICs |
一元素
(e-Elements) |
| 陳有毅 |
Yu-Yi Chen |
MS14 |
Cluster-Error Correction for TSVs in 3D-ICs |
友達光電
(AUO) |
| 李祐任 |
Yu-Jen Lee |
MS14 |
On-Line At-Speed Real-Time TSV Repairing |
晨星半導體
(MStar) |
| 林易生 |
Yi-Sheng Lin |
MS15 |
LDPC for On-Line Interconnects in 3D-ICs |
Cadence
(益華) |
| 劉韋廷 |
Wei-Ting Liu |
MS15 |
Aging Monitoring for 3D-ICs |
(服役) |
| 林柏勳 |
Po-Shun Lin |
MS16 |
Pre-computation Based Remapping HYPERA Architecture for Memory Repair |
創達科技 |
| 陳振興 |
Wei-Ting Liu |
MS16 |
Dual-Symptom Aging Monitor for Data TSVs in 3D-ICs |
|
| 林毓乾 |
Yi-Sheng Lin |
碩二 |
Delay-Tolerant Clock TSVs in 3D-ICs |
|
| 李堃淵 |
Wei-Ting Liu |
碩二 |
Fault-Tolerant Power TSVs in 3D-ICs |
|
| 林靖威 |
Yi-Sheng Lin |
碩一 |
Design for Reliability of CORDIC-based FFT |
|
| 李宜珊 |
Wei-Ting Liu |
Sr.+ |
Design for Reliability of SerDes TSVs in HMC2.1 |
|
