Training Courses on VLSI/CAD Tools
|
| Course | Date | Lecturer |
| An Introduction of Lab Environment | 7/19(一)AM | Professor |
| Survey | 7/19(一)AM | 史景文 |
| Solaris: Workstation / Vi | 7/19(一)PM | 史景文 |
| Full-custom Design Flow : Virtuoso | 7/20(二) | 許庭碩 |
| Full-custom Design Flow : Laker | 7/21(三)AM | 李宗澤 |
| C Language | 7/21(三)PM | 王雲平、林佑達 |
| Hspice | 7/22(四)AM | 趙文浩 |
| Nanosim | 7/22(四)PM | 謝曜鍵 |
| Cell-based Design Flow : Astro / SOC Encounter | 7/26(一) | 溫又卿、林毓庭 |
| Verilog Coding Style and Guideline / NCSim / ARM | 7/27(二)AM | 張維翔、郭彥廷 |
| FPGA Rapid Prototyping Design Flow/Quartus/Xilinx | 7/27(二)PM | 吳佳臻 |
| Verdi/Debussy/nLint/Design Compiler Tutorial | 7/28(三) | 王雲平、林佑達 |
| Syntest : Prime Power Tutorial | 7/29(四)AM | 陸貴葉 |
| Matlab | 7/29(四)PM | 溫又卿、林毓庭 |