Training Courses on VLSI/CAD Tools

 

  • Date: 2009/07/13-07/23

  • Time: 9:00am-12:00, 1:00pm-4:00pm

  • Lectors: Senior Graduate Students

  • Objective:  Fresh Graduate Students, Senior Undergraduates

  • Place: Room 31214

  • Equipments and Environments

 

Course Date Lecturer
An Introduction of Lab Environment  7/13( 一 )AM Professor
Survey 7/13( 一 )AM 梁正勳
Solaris: Workstation / Vi 7/13( 一 )PM 陳品充
Full-custom Design Flow : Virtuoso  7/14( 二 ) 葉峻利
Full-custom Design Flow : Laker  7/15( 三 )AM 賴谷皇
C Language 7/15( 三 )PM 范勝杰
Hspice  7/16( 四 )AM 徐培鈞
Nanosim 7/16( 四 )PM 羅杰恩
Verilog Coding Style and Guideline / NCSim / ARM 7/17( 五 )AM 蔡世儒、靳松穎
FPGA Rapid Prototyping Design Flow/Quartus/Xilinx 7/17( 五 )PM 楊尚銘、鄭丞宏
Verdi/Debussy/nLint/Design Compiler Tutorial  7/20( 一 ) 黃世易
Cell-based Design Flow : Astro / SOC Encounter  7/21( 二 ) 許韋寧
Syntest : Prime Power Tutorial  7/22( 三 )AM 張智豪
Synopsys : TetraMax 7/22( 三 )PM 劉昭男
Matlab  7/23( 四 )AM 李泰輪