Major Research Topics

主要研究方向

  • 3D-IC Testing:

Besides the FinFET, 3D-IC is the major infrastructures for enduring the Moore Law for decades. Through-Silicon Vias (TSVs) are the most critical interconnects in the 3D-IC structures. The design for reliability of TSVs is one of your major researches.

  • 三維晶片測試:

三維晶片和鰭狀場效電晶體是克服物理極限、延長莫爾定律的兩大結構。對於三維晶片,其矽穿孔又是最關鍵的連線。我們主要對矽穿孔連線的可靠設計進行研究。

  • Memory Test and Repair:

Memory is one of the circuitry with the greatest growth in volume demand. We are interested in the high-speed testing methodology and high-yield memory repairing techniques.

  • 記憶體測試與修復:

記憶體為容量需求成長最快的電路。我們主要對二維記憶體進行快速測試與高良率修復方面的研究。

  • Low Power Technologies for SoC Testing:

Power dissipation during testing is at least 2 times of that in normal mode.  We have developed many technologies to reduce the average and the peak power dissipation during test.  We also have fruitful results in transition-based power simulation and estimation

  • 系統晶片之低功耗測試:

晶片於測試時的功率消耗最少在正常模式時的兩倍。本研究團隊已研究出數種有效降低測試時平均功耗與尖峰功耗的技術。 我們對狀態轉移式的功耗模擬評估也有豐碩成果。

  • Low Leakage Design:

Our research also includes power management and low leakage design.  We focus on the supply-gating current spike reduction, MTCMOS sleep transistor allocation and low power logic design.

  • 低功(低漏電功耗)設計:

我們的研究較偏重在功耗管理技術、電源開關尖峰電流的預估與降低技術、多門檻電壓與電源開關電晶體配置技術、與低功低漏電流邏輯之設計。

  • Time-to-Digital and Jitter Measurement:

Our research also includes some in mixed-signal design.  We are interested in developing small-area low-power digital designs to measure time including T2D, jitter measurer, and the BIST for DPWM and PLLs.

  • 時間數位轉換與抖動量測:

我們的研究包含部份混合訊號方面的設計。我們的興趣包括對於發展低面積低功耗、用於測量時間、數位脈寬調變與鎖向迴路等電路的內建自我測試。