Syllabus
Google Meet: HDL, E404 https://meet.google.com/ykb-ptoy-xha
Course Title: Hardware Description Language (硬體描述語言, using Verilog)
Course No. 53022
Semester: Fall, 2021
Time and Classroom: Thu. +8:30-9:05-12:00 (E406)
Credits: 3
Lector: Professor Tsung-Chu Huang (黃宗柱)
Email: tch@cc.ncue.edu.tw
Tel. (04)723-2105 ext. 8384
Website: http://testlab.ncue.edu.tw/tch
NCUE Cloud: https://dlearn.ncue.edu.tw
Cloud: https://drive.google.com/drive/folders/1Efe5Tc_K1mMU0w6UK_4p-l1eN1Q0fxoU?usp=sharing (copy link and paste to browser; press leave or try IE if not download post zip)
Textbook and References
Textbook:
Samir Palnitkar. "Verilog HDL -- A Guide to Digital Design and Synthesis." Prentice Hall, 1999. (中譯版: 黃英叡等編, 全華, ISBN: 9572125176)
林灶生、劉紹漢編著,"Verilog FPGA晶片設計",ISBN:9572144456, 全華,2004。
Reference:
Michael D. Ciletti. "Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL." ISBN: 0139773983, Prentice Hall, 1999.
Mark Gordon Arnold. "Verilog Digital Computer Design -- Algorithms into Hardware." ISBN: 0136392539, Prentice Hall PTR, 1999. (中譯版: 楊紹聖等編, 全華, ISBN: 9572131176)
Schedule and Contents (To be revised)
Week 1 Introduction to TSMC, Overviews on HDLs [PPT] (Verilogger, SynaptiCAD) (Download and watch ModelSim Tutorials) (Lab1) (MP4)
Week 2 Y-Chart, Quick Tutorials [PPT], Installation Quartus II + ModelSim Golden-Test of Adders. (Lab2) [MP4]
Week 3 Four Models, (Exercising Lab 3-4), Modules and Ports in Verilog [PPT](Videos on Basic Library Simulation Flow using ModelSim) [MP4]
Week 4 Logic Synthesis, Algorithmic State Machine [PPT] [MP4]
Week 5 Rapid Prototyping using Verilog/Quartus II. (Exercising Lab 5-6) [MP4]
Week 6 Function, Task, Assignment, and Finite State Machine [PPT] (Lab7) [MP4]
Week 7 Practices on Timing Simulation (Lab8 ) [MP4]
Week 8 Practices and reviews for midterm exam. (Lab9) [MP4]
Week 9 Midterm Exam (Closed-book written test)
Week 10 Inertia Delay and Glitch, Counter-base FSM design [PPT] [MP4a, MP4b, MP4c] [Lab8, MP4Lab8]
Week 11 Tutorials to FPGA/SOPC Rapid Prototyping [PDF, PPT]
Week 12 (Athletic Games)
Week 13 Example of Scanned LED/KBD [PDF, PPT] UART Design using Verilog
Week 14 Introduction to Memory [PDF, PPT]
Week 15 Simple CPU Desing[PDF, PPT]
Week 16 Special Directives: generate, specify
Week 17 EDA Scripting: C-shell, TCL and SKILL
Week 18 Final exam
Criteria
Homework: 30% ► Second Midterm Exam
Midterm Exam: 30%
Final Exam: 30%
Term Project: 10% with a bonus 10%
-- 1~3 persons as a group design a simple but ISA-complete CPU with a simple keyboard and 7-Seg LEDs. (due last week)
Links
Open cores: http://www.opencores.org
Examples provided by Altera: http://www.altera.com/support/examples/verilog/verilog.html
The IEEE Verilog 1364-2001 Standard What's New, and Why You Need It.