SpringSoft nLint Evaluation Results

Soft IP

nLint check ability?

Verilog HDL Coding Guidelines

Naming Practice

[S.NC.1]  A file must contain at most one module unit

M2

y

[S.NC.2]  File name should be identical to design unit name

R

y

[S.NC.3] Only alphanumeric and underscore are allowed in naming

M1

y

[S.NC.4] Names starting with a letter

M2

y

[S.NC.5] Names can not be distinguishable in letter case only

M1

y

[S.NC.18] Verilog and VHDL keywords are prohibited

M1

y

[S.NC.19] The length of signal names does not exceed 32 characters

M2

y

[S.NC.23] Consistent ordering of bits for describing multibit buses

M2

y

Coding Style

[S.CS.3] Use a separate line for each HDL statement

M1

y

[S.CS.5] Preserve port order

M2

y

[S.CS.10] Use explicit port mapping instead of positional association in module instantiation

M1

y

[S.CS.11] Avoid expression in port connections

M1

y

[S.CS.14] Wire must be explicitly declared

M1

y

[S.CS.15] Operand size must match

M1

y

[S.CS.16] Expression in condition should be 1- bit value

R

y

Synthesis Related

[S.SYN.1] Use only synthesizable statement

M1

y

[S.SYN.1.1] Waveform statement are prohibited

M1

y

[S.SYN.1.2] System task and function for simulation (e.g. $display, $monitor, $printf, …) are prohibited

M1

y

[S.SYN.1.3] Wait statement and # delay statement are prohibited

M1

y

[S.SYN.1.4] Data type of real and event are prohibited

M1

y

[S.SYN.1.5] Only one clock per always sensitivity list

M1

y

[S.SYN.1.6] Loop must be in a static range

M1

y

[S.SYN.3] Avoid full_case and parallel_case synthesis directive statement

M2

y

[S.SYN.4] Specify code fragment for combinational logic completely

M2

y

[S.SYN.5] Verilog primitives are prohibited

M1

y

[S.SYN.6] All unused module inputs must be driven

M1

y

[S.SYN.8] Avoid top level glue logic

M2

y

[S.SYN.9] Incomplete case statements should have default case assignments

M2

y

Static Timing Analysis

[S.STA.1] Avoid Combinational feedback loop

M2

y

[S.STA.5] Avoid clock as data

M2

y

[S.STA.6] Avoid using latches

M2

y

Simulation

[S.SIM.1] Use non-blocking assignments in sequential always block

M1

y

[S.SIM.2] Use blocking assignments in combinational always block

M1

y

[S.SIM.3] Avoid missing sensitivity lists in combinational always block

M1

y

[S.SIM.4] Avoid redundant sensitivity lists

M1

y

[S.SIM.6] Do not assign signals don't care (x) value

M1

y

[S.SIM.7] Avoid using delay assignment

M1

y

Design for Test

[S.DFT.2] Avoid bi-directional nets

M2

y

[S.DFT.3] Avoid latches

M2

y

[S.DFT.4] Avoid using both edges of clocks

M2

y

[S.DFT.5] Avoid gating clocks

M2

y

[S.DFT.6] Avoid internal generated clocks

M2

y

[S.DFT.7] Avoid internal generated set/reset signals

M2

y

[S.DFT.9] Avoid combinational loop

M2

y