Syllabus
Course Title: Design for Testability (可測性積體電路設計)
Course No. 64041
Semester: Spring, 2005
Time and Classroom: Mon. 13:00pm-13:50pm (31303), Thu. 15:05pm-16:50pm (31217)
Credits: 3
Lector: Associate Professor Tsung-Chu Huang (黃宗柱)
Email: tch@cc.ncue.edu.tw
Tel. 7135896 ext. 110, Lab. (04)7232105 ext. 7131
Office: Tentative Office (Asking 7232105 ext. 7105 for details)
Website: http://163.23.223.30/tch
Textbook and References
Textbook:
M. Bushnell & V.D. Agrawal. "Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits." 2000.
Reference:
M. Abramovici, M. A. Breuer and A. D. Friedman. Digital System Testing and Testable Design." IEEE Press, 1993 (ISBN: 0-71678179-4).
Schedule and Contents [Download Acrobat Reader for PDF] [MS Office XP is suggested for viewing PPT]
Note: Remember to initiate the subject of your email for homework by [HW], e.g., Subject: [HW]s9345678, homework2.
[Lectures in Weeks 1-7, 10-11], [Lectures in other weeks will be handed out in class]
Week 1 Overviews: Introduction to VLSI Testing
Week 2 Review: Fault Modeling
Week 3 Review: Logic Simulation and Fault Simulation
Week 4 Review: Testing for Stuck-at Faults and Experiments using ATPG
Week 5 Testability and Experiments using TurboScan/asic123
Week 6 Scan-Based Design
Week 7 Boundary Scan
Week 8 Specific Scan Architectures
Week 9 Midterm Exam
Week 10 Compression Techniques
Week 11 Built-In Self-Test
Week 12 Specific BIST Architectures
Week 13 Special topic: Design for Low Power Scan
Week 14 Special topic: Design for Low Power Scan (Experiment 1)
Week 15 Special topic: Design for Low Power Scan (Experiment 2)
Week 16 Special topic: Introduction to Design for SoC Testing (1)
Week 17 Special topic: Introduction to Design for SoC Testing (2)
Week 18 Final Exam
Criteria
Homework: 10%
Midterm Exam: 30%
Final Exam: 30%
Term Project: 30%