Syllabus
Course Title: CPU Design (中央處理單元設計)
Course No. 64034
Semester: Spring, 2005
Time and Classroom: Wed.. 9:05am-12:00am (31218)
Credits: 3
Lector: Associate Professor Tsung-Chu Huang (黃宗柱)
Email: tch@cc.ncue.edu.tw
7135896 ext. 110, Lab. (04)7232105 ext. 7131
Office: Tentative Office (Asking 7232105 ext. 7105 for details)
Website: http://163.23.223.30/tch
Textbook and References
Textbook:
M. G. Arnold. Verilog Digital Computer Design -- Algorithm into Hardware. NJ: Prentice Hall. ISBN:0-13-639253-9. 1999.
Reference:
Kai Huang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, 1993.
ARM, "Arm Architecture Reference Manual," http://www.arm.com
Simon Segars, ”The ARM9 Family – High performance Microprocessors for Embedded Applications” Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference, pp:230-235,1998.
D. A. Patterson and J. L. Hennessy. Computer Organization & Design--The Hardware/Software Interface. Morgan Kaufmann, 2002.
MIPS, MIPS Series User Manual. http://www.mips.com
Alavoor Vasudevan. CPU-Design-Howto.
Schedule and Contents [Download Acrobat Reader for PDF] [MS Office XP is suggested for viewing PPT]
Note: Remember to initiate the subject of your email for homework by [HW], e.g., Subject: [HW]s9345678, homework2.
Week 1 Overviews; Introduction to History of CPU Design; Reviews on Verilog HDL, Instruction Set Architecture
Week 2 Introduction to Simple Computer Architecture, ALU/Datapath Design: Adders, Multipliers, Shifters, Comparators
Week 3 Sequencer Style: Finite-State-Machine (Experiment: SAP3X5)
Week 4 Sequencer Style: Algorithmic-State-Machine (Experiment: PDP8)
Week 5 Sequencer Style: Microprogramming
Week 6 Case Study: miniMIPS -- from ISA, I-format, OP-coding, von Neumann arch, concept of MCU and Pipeline to Design
Week 7 (Tomb-sweeping day)
Week 8 Pipeline, Pipelined Datapath, Forwarding and Superscalar
Week 9 Midterm Exam, Practice (MIPS32)
Week 10 Introduction to CPU DIP Design (Lecture 1 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 11 Introduction to ARM Architecture (Lecture 2 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 12 CPU External BUS Interface AHB (Lecture 3 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 13 Processor core memory interface (Lecture 4 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 14 ARM Integer Instruction Set (Lecture 5 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 15 Instruction Encoding and Addressing Mode (Lecture 6 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 16 Pipeline Implementation (Lecture 7 courtesy of Prof. Chen, NCKU/SIP Consortium)
Week 17 CPU Testing (Lecture courtesy of Prof. Lee, NCKU/SIP Consortium)
Week 18 Final Exam
Criteria
Homework: 10%
Midterm Exam: 30%
Final Exam: 30%
Term Project: 30%