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# <center>Implementation of a Ring Oscilator on Xilinx PYNQ-Z1</center>
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<center> TestLab, NCUE, Taiwan</center>
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<center> 2020/11/28</center>

Implementation of a Ring Oscilator on Xilinx PYNQ-Z1

TestLab, NCUE, Taiwan
2020/11/28
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## (1) Create a New Slave AXI Lite IP

(1) Create a New Slave AXI Lite IP

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* Open Vivado HLx 2018.2 > Create Project <u>RingOsc</u> at *workspace/RingOsc/* > Next > Next > Next > Next > Select Board <u>Pynq-z1</u> > Next > Finish
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* Create Block Design > Add IP ZYNQ7 > Tools > Create and New Package IP > Next > Create a New AXI4 Periphal > Name <u>RingOsc</u> > Next > Next > Next Steps: <u>Edit IP</u> > Finish
  • Open Vivado HLx 2018.2 > Create Project RingOsc at workspace/RingOsc/ > Next > Next > Next > Next > Select Board Pynq-z1 > Next > Finish
  • Create Block Design > Add IP ZYNQ7 > Tools > Create and New Package IP > Next > Create a New AXI4 Periphal > Name RingOsc > Next > Next > Next Steps: Edit IP > Finish
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# * Double click to open RingOsc_v1_0_S00_AXI.v
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* Edit the tail after Line 369 as
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```verilog
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    // Add user logic here
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    reg    [63:0] Q;
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    reg    En, Clr;
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    always @( posedge S_AXI_ACLK )
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        case(slv_reg0 )
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            32'h0   : begin En <= 1'h0; Clr <= 1'h0; end
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            32'h1   : begin En <= 1'h1; Clr <= 1'h1; end          
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            32'h2   : begin En <= 1'h1; Clr <= 1'h0; end          
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        endcase
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    parameter N = 21;
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    wire  OscClk;
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    (*DONT_TOUCH= "true"*) wire [N-1:0] Inv;
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    assign  Inv[N-1:1] = ~ Inv[N-2:0];
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    nand    g1(Inv[0], En, Inv[N-1]);
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    assign  OscClk = Inv[N-1];
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    always @(posedge OscClk)
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        if (Clr == 1'h1) Q <= 64'h0;
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        else Q <= Q + 1'h1;
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    // User logic ends
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    always @(*)
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    begin
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          // Address decoding for reading registers
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          case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
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            2'h0   : reg_data_out <= slv_reg0;
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            2'h1   : reg_data_out <= Q[63:32];
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            2'h2   : reg_data_out <= Q[31:0];
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            2'h3   : reg_data_out <= slv_reg3;
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            default : reg_data_out <= 0;
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          endcase
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    end
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endmodule
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```
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* Review and Package > Re-Package IP > Yes

* Double click to open RingOsc_v1_0_S00_AXI.v

  • Edit the tail after Line 369 as
    // Add user logic here
    reg    [63:0] Q;
    reg    En, Clr;
    always @( posedge S_AXI_ACLK )
        case(slv_reg0 )
            32'h0   : begin En <= 1'h0; Clr <= 1'h0; end
            32'h1   : begin En <= 1'h1; Clr <= 1'h1; end           
            32'h2   : begin En <= 1'h1; Clr <= 1'h0; end           
        endcase

    parameter N = 21;
    wire  OscClk;
    (*DONT_TOUCH= "true"*) wire [N-1:0] Inv;
    assign  Inv[N-1:1] = ~ Inv[N-2:0];
    nand    g1(Inv[0], En, Inv[N-1]);
    assign  OscClk = Inv[N-1];

    always @(posedge OscClk)
        if (Clr == 1'h1) Q <= 64'h0;
        else Q <= Q + 1'h1;
    // User logic ends

    always @(*)
    begin
          // Address decoding for reading registers
          case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
            2'h0   : reg_data_out <= slv_reg0;
            2'h1   : reg_data_out <= Q[63:32];
            2'h2   : reg_data_out <= Q[31:0];
            2'h3   : reg_data_out <= slv_reg3;
            default : reg_data_out <= 0;
          endcase
    end
endmodule
  • Review and Package > Re-Package IP > Yes
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## (2) Incooperate the IP to Block Design
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* Add IP > RingOsc_V1.0 > Run Block Automation > OK > Run Connection Automation > OK > Regenerate Layout > Save > Validate

(2) Incooperate the IP to Block Design

  • Add IP > RingOsc_V1.0 > Run Block Automation > OK > Run Connection Automation > OK > Regenerate Layout > Save > Validate
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![image.png](attachment:image.png)

image.png

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* Keep note of the address of S00_AXI in Address Editor, 0x43C0_0000
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* Change the label from Design to Source > Right click RingOsc.bd > Create HDL Wrapper > OK
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* Generate Bitstream
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* Read the log and error message
  • Keep note of the address of S00_AXI in Address Editor, 0x43C0_0000
  • Change the label from Design to Source > Right click RingOsc.bd > Create HDL Wrapper > OK
  • Generate Bitstream
  • Read the log and error message
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## (3) Add Constraint Files
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* Directives for Design Constraints:
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|Level | Approach | Example |
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|----|----|----|
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|Normal|Variable Tappping|Combinational Circuit|
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|Generic synthesis|(*KEEP="TRUE"*)|Generic Logic|
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|Placement synthesis|(*DONT_TOUCH="TRUE"*)|Delayline|
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|Routing DRC|(*ALLOW_COMBINATORIAL_LOOPS="TRUE"*)|Ring Oscillator|
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|Full Custom|set_property LOC SLICE_X50Y151  [get_cells hierachy/inst.LUT]|Specific MSA|
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​
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* Without DRC constraints, you will get a suggestion as follows:
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```
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    [DRC LUTLP-1] Combinatorial Loop Alert: ...
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    'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'
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    One net in the loop is RingOsc_i/RingOsc_0/inst/RingOsc_v1_0_S00_AXI_inst/Inv[11].
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```    
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* This helps you to unroll and look up the complex hierarchy for next step.

(3) Add Constraint Files

  • Directives for Design Constraints:
Level Approach Example
Normal Variable Tappping Combinational Circuit
Generic synthesis (KEEP="TRUE") Generic Logic
Placement synthesis (DONT_TOUCH="TRUE") Delayline
Routing DRC (ALLOW_COMBINATORIAL_LOOPS="TRUE") Ring Oscillator
Full Custom set_property LOC SLICE_X50Y151 [get_cells hierachy/inst.LUT] Specific MSA
  • Without DRC constraints, you will get a suggestion as follows:
    [DRC LUTLP-1] Combinatorial Loop Alert: ...
    'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'
    One net in the loop is RingOsc_i/RingOsc_0/inst/RingOsc_v1_0_S00_AXI_inst/Inv[11].
  • This helps you to unroll and look up the complex hierarchy for next step.
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* Click Constraints > Right click constrs_1 > Add Sources > Add and Generate Constraints > Next > Create File < <u>RingOsc</u> > OK > Finish
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* Unroll Hierarchy /Design Sources/RingOsc_wrapper/RingOsc_i/RingOsc_0/
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* Under Label Sources > Click constrs_1 > Double click RingOsc.xdc to edit as follows:
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    **set_property ALLOW_COMBINATORIAL_LOOPS TRUE [ get_nets  RingOsc_i/RingOsc_0/inst/RingOsc_v1_0_S00_AXI_inst/Inv[11] ]**
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* Generate Bitstream
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* File > Explort Bitstream to E:/Work/Vivado/RingOsc/RingOsc.bit
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* In the TCL Console > *write_bd_tcl  Workspace/Vivado/RingOsc/RingOsc.tcl*
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* File > Export Hardware, one .hwh can be found in Workspace\Vivado\RingOsc\RingOsc.srcs\sources_1\bd\RingOsc\hw_handoff.
  • Click Constraints > Right click constrs_1 > Add Sources > Add and Generate Constraints > Next > Create File < RingOsc > OK > Finish
  • Unroll Hierarchy /Design Sources/RingOsc_wrapper/RingOsc_i/RingOsc_0/

  • Under Label Sources > Click constrs_1 > Double click RingOsc.xdc to edit as follows:

    set_property ALLOW_COMBINATORIAL_LOOPS TRUE [ get_nets RingOsc_i/RingOsc_0/inst/RingOsc_v1_0_S00_AXI_inst/Inv[11] ]

  • Generate Bitstream

  • File > Explort Bitstream to E:/Work/Vivado/RingOsc/RingOsc.bit
  • In the TCL Console > write_bd_tcl Workspace/Vivado/RingOsc/RingOsc.tcl
  • File > Export Hardware, one .hwh can be found in Workspace\Vivado\RingOsc\RingOsc.srcs\sources_1\bd\RingOsc\hw_handoff.
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## (4) Report Inspection
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* Schematics:
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![image.png](attachment:image.png)

(4) Report Inspection

  • Schematics: image.png
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* Inverter ring and driven tree
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![image.png](attachment:image.png)
  • Inverter ring and driven tree

image.png

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* Pyhsical Layout
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![image.png](attachment:image.png)
  • Pyhsical Layout

image.png

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## (5) Testing the RingOsc IP
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* Rename all .bit, .tcl and .hwh file as the same name > Upload to PYNQ here.

(5) Testing the RingOsc IP

  • Rename all .bit, .tcl and .hwh file as the same name > Upload to PYNQ here.
In [7]:
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%matplotlib inline
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import matplotlib.pyplot as plt
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import numpy as np
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import time
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​
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from pynq import Overlay
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from pynq import MMIO
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overlay = Overlay('RingOsc.bit')
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ip = MMIO(0x43C00000, 0x10000)
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​
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ip.write(0, 0) # reset
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ip.write(0, 1) # enable oscillating and reset counter
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ip.write(0, 2) # oscilating and counting
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x, y = [], []
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for i in range(100):
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    ip.write(0, 1) # enable oscillating and reset counter
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    ip.write(0, 2) # oscilating and counting
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    time.sleep(0.01)
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    n = ip.read(4) * (1<<32) + ip.read(8)
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    x.append(i)
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    y.append( n )
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plt.title('Frequency (Count per 10ms) with Ambles')
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plt.plot(x, y)
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plt.grid(True)
In [2]:
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ip.read(4), ip.read(8)
Out[2]:
(0, 353243443)
In [3]:
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ip.read(4), ip.read(8)
Out[3]:
(0, 406953378)
In [4]:
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ip.read(4), ip.read(8)
Out[4]:
(0, 446130631)
In [5]:
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ip.read(4), ip.read(8)
Out[5]:
(0, 489538343)
In [6]:
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ip.write(0, 1)
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ip.write(0, 2)
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ip.read(8)
Out[6]:
70478
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## (6) Applications
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* True Random Number Generator
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* Physical Unclonable Function (PUF) for Hardware Security
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* Thermal Sensors
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* Aging Sensors
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* Voltage Drop and IDDQ Sensors (inaccurate)
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* Clock Generator for coarse applications
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* Digital Delay Lock Loop (rough due to $\Delta{f}/{f} > 2\%$)

(6) Applications

  • True Random Number Generator
  • Physical Unclonable Function (PUF) for Hardware Security
  • Thermal Sensors
  • Aging Sensors
  • Voltage Drop and IDDQ Sensors (inaccurate)
  • Clock Generator for coarse applications
  • Digital Delay Lock Loop (rough due to Δf/f>2%)