Final Program

Click here for download Program Brochure

Monday July 10th, 2017

Tutorials

14:00-17:30   Assembly Hall

Tutorial 1:  Challenges about Hardware Security

Professor Gang Qu, UMD, US

Abstract --

In this tutorial, we will study security and trust from the hardware perspective. Upon completing the course, students will understand the vulnerabilities in current digital system design flow and the physical attacks to these systems. They will learn that security starts from hardware design and be familiar with the tools and skills to build secure and trusted hardware.

Biography --

Professor Qu Gang received his M.S. and Ph.D. degrees from UCLA, both in Computer Science. Previously, he had studied Mathematics in the Univerisy of Science and Technology of China (USTC) and the University of Oklahoma. Dr. Qu is the co-director of the Embedded System Research Laboratory and the Wireless Sensor Laboratory. His primary research interests are in the area of embedded systems and VLSI (Very Large Scale Integration) CAD (Computer Aided Design) with focus on low power system design and hardware related security and trust. He studies optimization and combinatorial problems and applies his theoretical discovery to applications in VLSI CAD, wireless sensor network, bioinformatics, and cybersecurity. Dr. Qu and his research group are sponsored by AFOSR, ARO, DARPA, NSA-LTS, NSF, ONR, USDA; Cisco, Fujitsu Research, and Microsoft Research.

Tutorial 2:  Study on Soft Error Rate (SER): Past, Present, and Future

Professor Hung-Pin(Charles) Wen, NCTU

Abstract -- 

In this tutorial, we re-examine the soft-error effect caused by radiation-induced particles beyond the deep submicron regime. Considering the impact of process variations, voltage pulse widths of transient faults are found no longer monotonically diminishing after propagation, as they were formerly. As a result, the soft error rates in scaled electronic designs escape traditional static analysis and are seriously underestimated. A new concept of statistical soft error rate (SSER) is presented with analysis frameworks for coping with the aforementioned concerns. More advanced issues like aging will be covered if time permits.

Biography --

Charles H.-P. Wen received the Ph.D. degree in very-large-scale integration (VLSI) verification and test from the University of California, Santa Barbara, Santa Barbara, CA, USA, 2007. He is currently an Associate Professor with National Chiao Tung University, Hsinchu, Taiwan, and is a specialist in computer engineering. Over the past five years, his research has been focused on data mining/machine learning techniques to VLSI designs (especially on statistical soft error rates), software-defined networking and network function virtualization (SDN/NFV). Prof. Wen was also a recipient of the best paper awards from the 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012), the 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2015), the 30th and the 31th International Conference on Information Networking (ICOIN 2016 & ICOIN 2017), and the Distinguished Young Scholar Award of Taiwan IC Design Society in 2015.

VLSI Test Technology Forum (VTTF) (joint Meeting)

14:00-17:00   Meeting Room 3

Technical Session

Talk 1    TBD

Prof. Meng-Lieh Sheu, NCNU

Talk 2    TBD

Prof. Jwu-E Chen, NCU

Talk 3    "My Role Model"

Prof. Soon-Jyh Chang, NCKU

Talk 4 "IDEA: An integrated dependability enhancement architecture for flash memory storage systems."

Prof. Shyue-Kung Lu, NTUST

Discussions

Discussion 1    Progress of ITC-Asia-2017

Prof. Shi-Yu Huang, NTHU

Discussion 2    Progress of ATS-2017

Prof. Jin-Fu Li, NCU

Discussion 3    Progress of WRTLT2017

Prof. Shyue-Kung Lu, NTUST

Discussion 4    Next VTTFs

Prof. Tong-Yu Hsieh, NSYSU

Tuesday July 11th, 2017

Plenary Sessions  

Opening

9:00-9:10  Assembly Hall

Keynote Speech (1):  "Right Power Testing for Scan-Based BIST and Its Evaluation with TEG Chips"

Prof. Seiji Kajihara, KyuTech, Japan

Chair: Prof. Shyue-Kung Lu, NTUST

9:10-10:00  Assembly Hall

Abstract --

High power dissipation during scan-based logic BIST (LBIST) is a crucial issue that may lead to chip damage, cost increase, reliability degradation, or over-testing. Although many sophisticated low-power approaches were proposed in the past, it is still difficult to control the test power of LBIST to an appropriate level which is different depending on applications. This talk discusses a power-controlling method for LBIST that controls the toggle rate during scan-shift operation to an arbitrary level by modifying pseudo-random patterns. Furthermore the method maintains high fault coverage without increasing test time. Simulation-based experiments clearly demonstrate that the proposed method can flexibly control toggle rate, and evaluations on TEG chips show the effect on circuit delay by test power controlling.

Biography --

Seiji Kajihara received the B.S. and M.S. degrees from Hiroshima University, Japan, and the Ph.D. degree from Osaka University, Japan, in 1987, 1989, and 1992, respectively. From 1992 to 1995, he worked with Osaka University, as an Assistant Professor. In 1996, he joined the School of Computer Science and Systems Engineering of Kyushu Institute of Technology, Japan, where he is a Dean and Professor currently. His research interest includes logic testing and dependable systems. He received the Young Engineer Award from IEICE in 1997, the IEEE ITC2005 Most Significant Paper Award, and several Best Paper Awards from IEICE, IEEE WRTLT 2007, IEEE ATS 2016. Dr. Kajihara is a member of the IEEE and the IPSJ, and a fellow of the IEICE.

Invited Talk:

Director C.F. Wu, RealTek, Taiwan

Chair: Chair: Prof. Chih-Tsun Huang

10:00-10:50  Assembly Hall

Abstract --

A series of significant mergers and acquisitions indicates the mature of semiconductor industry.  Fabless companies, as part of the whole semiconductor industry, also face challenges to maintain continuous growth.  In this talk, we review the decision making of each and every stage of complex SoC design, from silicon to system, to find out opportunities for innovation.

Biography --

Chi-Feng Wu received the B.S. degree in 1996, the M.S. degree in 1998, and the Ph.D. degree in 2001, all in electrical engineering, from National Tsing Hua University (NTHU), Hsinchu, Taiwan.  His research interests include the design and test of VLSI cores and systems.  He is currently the Senior Director of R&D Center at Realtek Semiconductor Corp., Hsinchu, Taiwan, where he is responsible for design technology of processor and system-on-chip platform and IP outsourcing strategy.  He has published more than 20 research papers in these areas and is an inventor of 6 US patents.  He received the Outstanding Award in the IC/CAD Contest of Ministry of Education in 1999, the Best Paper Award in Professor Wen-Zen Shen Memorial Award of Taiwan IC Design Society in 2003, the Outstanding Employee Award of Hsinchu Science Park in 2013, and the Outstanding I.T. Elite Award in 2015.

Technical Sessions

(underscored for presenter)

Session 1: Clock Test/Synthesis and Debug/Verification
Chair: Prof. Ching-Hwa Cheng

11:10-12:10    Assembly Hall

S1-1: DLL-Assisted Clock Synchronization Method for Multi-Die ICs
Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai and Yung-Fa Chou
S1-2: A Silicon Debug Technique for Multiple Clock Domain Systems
Shuo-Lian Hong and Kuen-Jong Lee
S1-3: Exploring Domain Equivalence for Accelerating UPF-based Power Verification of RTL Designs
Chia-Hao Hsu and Charles H.-P. Wen
S1-4: Testing Clock Distribution Networks

Sying-Jyan Wang, Hsiang-Hsueh Chen, Chih-Hung Lien and Katherine Shu-Min Li

Session 2: Memory Test and Repair
Chair: Prof. Jing-Jia Liou

13:30-14:15    Assembly Hall

S2-1: Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM
Kuan-Wei Hou and Cheng-Wen Wu
S2-2: Efficient Built-In Self-Test Scheme for Multi-Channel DRAMs
Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai and Yung-Fa Chou
S2-3: Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories
Shyue-Kung Lu, Shu-Chi Yu, and Masaki Hashizume

Session 3: Error Detection and Correction
Chair: Prof. Chun-Lung Hsu

14:20-15:20    Assembly Hall

S3-1: Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops
Dave Y.-W. Lin and Charles H.-P. Wen
S3-2: Low-Latency Multiple-Cluster Error Correction for Critical Interconnect Arrays
Yi-Shan Li, Sing-Ni Huang and Tsung-Chu Huang
S3-3: A Hybrid Concurrent Error Detection Scheme for Simultaneous Improvement on Probability of Detection and Diagnosability
Chih-Hao Wang and Tong-Yu Hsieh
S3-4: An Image Error-Tolerability Test Method for Face Detection Applications
Tong-Yu Hsieh, Chao-Ru Chen and Tai-Ang Cheng

Poster Session (Post from 09:00 to 17:50)
Chair: Prof. Yingchieh Ho

15:20-16:00 Assembly Hall

SP-1: Multiple-TSV Schemes for Lagging-Defect Tolerant Clock-Delivery in 3D ICs
Yu-Chien Lin and Tsung-Chu Huang
SP-2: A Defect-Tolerant Multi-TSV Structure and Placement for Power-Grids in 3D ICs
Kun-Yuan Li, Mong-Lin Li and Tsung-Chu Huang
SP-3: The Rainbow Transformed from a Set of Uniform-defect Wafer Maps
Jwu-E Chen, Hsing-Chung Liang, Ching-Ju Lin and Ya-Syuan Wu
SP-4: Detection for Stealthy Combinational Hardware Trojans
Sying-Jyan Wang, Jhih-Yu Wei, Shih-Heng Huang, Katherine Shu-Min Li (presented by Bo-Jyun Hou)
SP-5: Digital Rights Management for Paper-Based Microfluidic Biochips
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li and Tsung-Yi Ho

SP-6: The Image Stitching Performance and Quality Improve Techniques

Nguyen Van Thang and Ching-Hwa Cheng

Session 4: Scan-Test and FPGA Formatter
Chair: Prof. Jwu-E Chen

16:00-16:45 Assembly Hall

S4-1: Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation
Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang and Terry Kuo
S4-2: DR-scan: Dual-rail Asynchronous Scan DfT and ATPG
Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chien-Mo Li and Chia-Cheng Pai
S4-3: The Interconnection Evaluation and Reconfiguration Mechanisms for 3D-Stacking System
Ching-Hwa Cheng

Session 5: Mixed-Signal
Chair: Prof. Soon-Jyh Chang

16:50-17:50 Assembly Hall

S5-1: A Resistor-String Digital-to-Analog Converter Based Waveform Generator
Hsin-Wen Ting, Jian-Zhou Yan, Hsin-Ying Wu and Zi-Tao Wu
S5-2: Co-Placement Optimization of Cyber-Physical Digital Microfluidic Biochips for Testing
Jian-De Li and Sying-Jyan Wang
S5-3: Lifetime Estimation of NBTI Effects for Manufactured Circuits
Chia-Hau Hsu, Jing-Jia Liou, Zih Huan Gao and Ting-Shuo Hsu
S5-4: Process-Compensated Track-and-Hold Circuit with Leakage Suppression in Low-voltage SAR Analog-to-Digital Converters
Yingchieh Ho and Yan-Ze Lin (presented by Yi-Hong Yu)

Wednesday July 12th, 2017

Keynote Speech (2): "Eye in the Sky -- Health Condition Monitoring for IoT Devices in the Field."

9:00-9:50  Assembly Hall

Prof. S.-Y. Huang, NTHU, Taiwan

Chair: Prof. Jin-Fu Li

Abstract -- Dr. Shi-Yu Huang received his B.S. and M.S. degrees in Electrical Engineering from National Taiwan University in 1988 and 1992, respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of California, Santa Barbara, in 1997. He joined the faculty of Electrical Engineering Department, National Tsing Hua University, Taiwan, in 1999, where he is currently Professor. His research interests broadly cover VLSI design, automation, and testing, with prior experiences on formal verification, power estimation, fault diagnosis, and resilient nanometer SRAM Design. More recently, his research concentrates on cell-based timing circuit designs and their compiler techniques, including Phase-Locked Loop (PLL), Delay-Locked Loop (DLL), Time-to-Digital Converter (TDC), and Programmable Phase-Shifter (PPS), and the applications of these timing circuits to the parametric fault testing and reliability enhancement for 3D-ICs or multi-die integrated ICs. He has published more than 140 refereed technical papers.       Dr. Huang ever co-founded a company, TinnoTek Inc. (2007-2012), specializing a cell-based PLL compiler and system-level power estimation tools. He is a recipient of the Best-Presentation Award from VLSI-DAT in 2006, the Best-Paper Awards from VLSI-DAT in 2013, and ATS in 2014, respectively. Dr. Huang has actively served in the IEEE community, as Program Chair or Co-Chair for 5 IEEE conferences. He is a senior member of IEEE and has been serving in the Editorial Board of IEEE Trans. on Computers as an Associate Editor since 2015.

Biography -- Internet of Things (IoT) devices have found their ways into various applications in smart homes, offices, automobiles, factories, and cities. These new types of devices not only demand new design and manufacturing methodologies, but also bring numerous challenges from the general testing point of view - such as zero-defect quality, high reliability, and long lifetime, etc. To satisfy all these objectives, not only the offline test methods are needed, but also the online monitoring schemes, so that the health condition of an IoT device can be monitored continually throughout its lifetime. By doing so, a run-time failure threat can be detected, diagnosed, and then averted just-in-time via some reconfiguration or replacement procedure to minimize the chance of sudden collapse. In this talk, we will first overview a number of online health condition monitoring schemes and then present a prototype system with some fabricated Design-for-Health-Monitoring circuitry. We will demonstrate how the dynamic supply voltage of an IoT device in the field can be monitored from the cloud, by riding the free wireless communication function provided by the device itself.

Academic-Industrial Panel

10:10-11:30  Assembly Hall

Chair: Charles H.-P. Wen, NCTU

Panelists: 

Best Paper Award

11:30-11:40  Assembly Hall

Farewell

11:40-11:50  Assembly Hall

General Chairs and TP Chair of Next VTTW