Call-for-Paper Flyer

Paper Submission:

Submission Web Page:

Paper submissions should be camera-ready manuscripts, not exceeding six two-column pages (including a 50 to 200-word abstract, figures, tables, and bibliography) in pdf format. The submission will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. The registration of at least one author is required for each presented paper; all presentations should be given in English.


Important Dates

Paper submission deadline: June 15, 2017

Notification of acceptance: June 20, 2017



Contributions related to electronic circuit and system testing are solicited. Topics of interest include, but are not limited to:

¡ETest generation & fault simulation
¡EDesign for testability and reliability
¡EFault tolerance and error correction
¡EFailure analysis & fault modeling
¡EAnalog/mixed-signal & RF testing
¡ECPU testing
¡EMemory testing and repair
¡EHigh-speed I/O testing
¡ESystem-level testing

¡EBuilt-in self-test
¡EESL testing
¡ESilicon Debug and Diagnosis
¡ETest economics
¡EWafer-level testing
¡ESoC/SiP/3D IC testing
¡EInterconnect testing and repair
¡EOn-chip monitoring
¡EYield and Reliability Enhancement